Integrated half-bridge circuit with low side and high side composite switches
View Patent ↗There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches. The first and second III-N FETs are normally ON FETs, and the low side composite switch and the high side composite switch are normally OFF switches
1. An integrated half-bridge circuit including a low side composite switch and a high side composite switch, said integrated half-bridge circuit comprising:
a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET;
a second group IV FET stacked over said III-N body;
said first group IV FET cascoded with said first III-N FET to provide one of said low side and said high side composite switches, and said second group IV FET cascoded with said second III-N FET to provide the other of said low side and said high side composite switches;
wherein said first and second III-N FETs are normally ON FETs, and wherein said low side composite switch and said high side composite switch are normally OFF switches.
2. The integrated half-bridge circuit of claim 1 , wherein a source of said first III-N FET is coupled to a drain of said first group IV FET by a through-semiconductor via (TSV) through said III-N body.
3. The integrated half-bridge circuit of claim 1 , wherein a drain of said second group IV FET on a bottom side of said second group IV FET is stacked on a source of said second III-N FET.
4. The integrated half-bridge circuit of claim 1 , wherein said first group IV FET, said second group IV FET, and said first and second III-N FETs are monolithically integrated.
5. The integrated half-bridge circuit of claim 1 , wherein at least one of said first and second group IV FETs comprises a lateral channel FET.
6. The integrated half-bridge circuit of claim 1 , wherein at least one of said first and second group IV FETs comprises a vertical channel FET.
7. The integrated half-bridge circuit of claim 1 , wherein said first and second group IV FETs comprise low-voltage silicon FETs.
8. The integrated half-bridge circuit of claim 1 , wherein said first and second III-N FETs comprise high-voltage III-N FETs.
9. The integrated half-bridge circuit of claim 1 , wherein said first and second III-N FETs comprise III-N high electron mobility transistors (HEMTs).
10. An integrated half-bridge circuit including a low side composite switch and a high side composite switch, said integrated half-bridge circuit comprising:
a first group IV field-effect transistor (FET) stacked under a substrate;
a III-N body including first and second III-N FETs situated over said substrate;
a second group IV FET stacked over said III-N body;
said first group IV FET cascoded with said first III-N FET to provide one of said low side and said high side composite switches, and said second group IV FET cascoded with said second III-N FET to provide the other of said low side and said high side composite switches;
wherein said first and second III-N FETs are normally ON FETs, and wherein said low side composite switch and said high side composite switch are normally OFF switches.
11. The integrated half-bridge circuit of claim 10 , wherein said first III-N FET is coupled to said first group IV FET by a through-semiconductor via (TSV).
12. The integrated half-bridge circuit of claim 10 , wherein said TSV extends through said substrate and contacts a drain of said first group IV FET.
13. The integrated half-bridge circuit of claim 10 , wherein a drain of said second group IV FET on a bottom side of said second group IV FET is stacked on a source of said second III-N FET.
14. The integrated half-bridge circuit of claim 10 , wherein said first and second III-N FETs are monolithically integrated.
15. The integrated half-bridge circuit of claim 10 , wherein said first and second group IV FETs comprise silicon FETs.
16. The integrated half-bridge circuit of claim 10 , wherein said first and second group IV FETs comprise low-voltage group IV FETs, and wherein said first and second III-N FETs comprise high-voltage III-N FETs.
17. The integrated half-bridge circuit of claim 10 , wherein said first and second III-N FETs comprise III-N high electron mobility transistors (HEMTs).
18. The integrated half-bridge circuit of claim 10 , wherein said first and second III-N FETs and one of said first and second group IV FETs are monolithically integrated.
19. The integrated half-bridge circuit of claim 10 , wherein at least one of said first and second group IV FETs comprises a lateral channel FET.
20. The integrated half-bridge circuit of claim 10 , wherein at least one of said first and second group IV FETs comprises a vertical channel FET.