Parallel bitline nonvolatile memory employing channel-based processing technology

1. A memory, comprising:

a memory cell having a gate node, a source node and a drain node, wherein the gate node is connected to a wordline of the memory, the source node is connected to a local source line of the memory, and the drain node is connected to a local data line of the memory; and

a channel-based processing component configured to program the memory cell and inhibit programming of a second memory cell on the wordline of the memory, the channel-based processing component configured to ground the local source line and the local data line in conjunction with programming the memory cell, and configured to float a second local source line and a second local data line connected to the second memory cell in conjunction with inhibiting programming of the second memory cell.

2. The memory of claim 1 , the second memory cell comprising a second source node that is connected to the second local source line.

3. The memory of claim 1 , the second memory cell comprising a second drain node that is connected to the second local data line.

4. The memory of claim 1 , wherein the local source line is connected to a common source line of the memory via a select transistor and the second local source line is connected to the common source line via a second select transistor.

5. The memory of claim 1 , wherein the local data line and the second local data line are connected to respective global data lines of the memory.

6. The memory of claim 1 , further comprising an array of the memory cells having respective gate nodes connected to respective ones of a set of wordlines of the memory.

7. The memory of claim 6 , the array of memory cells having respective source nodes connected to the local source line of the memory.

8. The memory of claim 6 , the array of memory cells having respective drain nodes connected to the local data line of the memory.

9. The memory of claim 6 , wherein the array of memory cells includes the memory cell.

10. The memory of claim 9 , further comprising a second array of memory cells having respective gate nodes connected to the wordline of the memory, having respective source nodes connected to respective ones of a set of local source lines of the memory that includes the local source line and the second local source line, and having respective drain nodes connected to respective ones of a set of local data lines of the memory that includes the local data line and the second local data line, the second array of memory cells comprising the memory cell and the second memory cell.

11. The memory of claim 1 , wherein the memory cell or the second memory cell is a charge trap NOR transistor.

12. The memory of claim 1 , wherein the memory cell or the second memory cell is a multi-level cell configured to store more than a single bit of digital information.

13. A method, comprising:

applying around zero volts to a first local source line and a first local data line connected to first memory cell of a memory device;

floating a second local source line and a second local data line connected to a second memory cell of the memory device, facilitating program inhibiting of the second memory cell; and

applying a program voltage to a wordline of the memory device connected at least to a gate of the first memory cell and to a gate of the second memory cell to facilitate programming the memory cell and inhibiting programming of the second memory cell.

14. The method of claim 13 , further comprising applying a moderate voltage, less than the program voltage and greater than zero volts, to a second wordline of the memory device.

15. The method of claim 13 , further comprising floating the first local source line and to the first local data line to facilitate inhibiting programming of the first memory cell.

16. The method of claim 15 , further comprising applying around zero volts to the second local source line and the second local data line to facilitate programming the second memory cell.