Methods and systems of impedance source semiconductor device protection
View Patent ↗An electrical network configured to suppress voltage transients is disclosed. The network includes a capacitor and an electrical impedance in parallel with a diode. The capacitor is in series with the parallel connected diode and electrical impedance, and the electrical network is configured to suppress voltage transients occurring across the series combination of the capacitor and the parallel connected diode and electrical impedance.
1. A Z source network, comprising:
positive and negative input terminals;
a shunt capacitor connected to the positive and negative input terminals;
a diode having an anode connected to the positive input terminal and a cathode connected to an internal node of the Z source network;
positive and negative output terminals;
a first inductor connected to the inner node and to the positive output terminal;
a first capacitor connected to the inner node and to the negative output terminal;
a second inductor connected to the negative input terminal and to the negative output terminal;
a second capacitor connected to the negative input terminal and the positive output terminal; and
an electrical network configured to suppress voltage transients, the electrical network comprising:
a capacitor; and
an electrical impedance in parallel with a diode, wherein the capacitor is in series with the parallel connected diode and electrical impedance,
wherein the electrical network is configured to suppress voltage transients occurring across the positive and negative input terminals.
2. The electrical network of claim 1 , wherein the electrical impedance comprises a resistor.
3. The electrical network of claim 2 , wherein the electrical impedance further comprises at least one of an additional resistor, a capacitor, and an inductor.
4. The electrical network of claim 1 , wherein the electrical impedance is actively controlled.
5. The electrical network of claim 1 , further comprising an energy storage element or an energy conversion element in parallel with the capacitor.
6. A Z source network, comprising:
positive and negative input terminals;
a shunt capacitor connected to the positive and negative input terminals;
a diode having an anode connected to the positive input terminal and a cathode connected to an internal node of the Z source network;
positive and negative output terminals;
a first inductor connected to the inner node and to the positive output terminal;
a first capacitor connected to the inner node and to the negative output terminal;
a second inductor connected to the negative input terminal and to the negative output terminal;
a second capacitor connected to the negative input terminal and the positive output terminal; and
an electrical network configured to suppress voltage transients, the electrical network comprising:
a first capacitor;
an electrical impedance in parallel with a diode, wherein the first capacitor is in series with the parallel connected diode and electrical impedance; and
second and third capacitors, wherein the second and third capacitors are in series with the first capacitor and the parallel connected diode and electrical impedance,
wherein the electrical network is configured to suppress voltage transients occurring across the positive and negative output terminals.
7. The electrical network of claim 6 , wherein the electrical impedance comprises a resistor.
8. The electrical network of claim 7 , wherein the electrical impedance further comprises at least one of an additional resistor, a capacitor, and an inductor.
9. The electrical network of claim 6 , wherein the electrical impedance is actively controlled.
10. The electrical network of claim 6 , further comprising an energy storage element or an energy conversion element in parallel with the capacitor.
11. The electrical network of claim 6 , wherein the first capacitor, the electrical impedance, the diode, the second capacitor, and the third capacitor are integrated in a package.
12. The electrical network of claim 11 , wherein the positive and negative output terminals are connected to first and second terminals of a load, and wherein the package is connected to the load at the first and second terminals.