Oversampled receiver for transition encoded signaling
A receiver includes a multiphase clock having multiple clock edges, the clock edges being time staggered for the multiphase clock. The receiver further includes circuitry configured to receive a multi-wire transitional coded signal, sample, at each clock edge of the multiphase clock, the multi-wire transitional coded signal to obtain a sample sequence, and output a symbol for each transition in the sample sequence to obtain an output receiver sequence. The number of clock edges is greater than the number of symbols.
1. A receiver comprising:
a multiphase clock having a plurality of clock edges, the plurality of clock edges being time staggered for the multiphase clock; and
circuitry configured to:
receive a multi-wire transitional coded signal,
sample, at each clock edge of the multiphase clock, the multi-wire transitional coded signal to obtain a sample sequence, and
output a symbol for each transition in the sample sequence to obtain an output receiver sequence,
wherein a number of clock edges is greater than the number of symbols.
2. The receiver of claim 1 , wherein the circuitry is further configured to:
detect bad symbols in the sample sequence.
3. The receiver of claim 2 , wherein sampling the multi-wire transitional coded signal comprises:
obtaining a sequential set of matching symbols triggered by a clock edge of the multi-phase clock, and
wherein detecting bad symbols comprises:
dropping the sequential set of matching symbols when a number of the sequential set of matching symbols satisfies a drop threshold.
4. The receiver of claim 2 , wherein detecting bad symbols comprises:
dropping a sample when a length of time to sample the multi-wire transitional coded signal and obtain the sample satisfies a drop threshold.
5. The receiver of claim 2 , wherein sampling at a clock edge of the multiphase clock comprises:
sampling, by multiple samplers, the multi-wire transitional coded signal to obtain a plurality of symbols for the clock edge,
wherein detecting bad symbols comprises:
using a voting scheme to determine whether the plurality of symbols is valid.
6. The receiver of claim 5 , wherein using the voting scheme comprises selecting a highest frequency symbol from the plurality of symbols to add to the sample sequence.
7. The receiver of claim 6 , wherein the highest frequency symbol is selected when a frequency of the highest frequency symbol satisfies a keep threshold.
8. A method comprising:
receiving a multi-wire transitional coded signal;
sampling, at each clock edge of a multiphase clock having a plurality of clock edges, the multi-wire transitional coded signal to obtain a sample sequence, wherein the plurality of clock edges are time staggered for the multiphase clock; and
output a symbol for each transition in the sample sequence to obtain an output receiver sequence,
wherein a number of clock edges is greater than the number of symbols.
9. The method of claim 8 , further comprising:
detecting bad symbols in the sample sequence.
10. The method of claim 9 , wherein sampling the multi-wire transitional coded signal comprises:
obtaining a sequential set of matching symbols triggered by a clock edge of the multi-phase clock, and
wherein detecting bad symbols comprises:
dropping the sequential set of matching symbols when a number of the sequential set of matching symbols satisfies a drop threshold.
11. The method of claim 9 , wherein detecting bad symbols comprises:
dropping a sample when a length of time to sample the multi-wire transitional coded signal and obtain the sample satisfies a drop threshold.
12. The method of claim 9 , wherein sampling at a clock edge of the multiphase clock comprises:
sampling, by multiple samplers, the multi-wire transitional coded signal to obtain a plurality of symbols for the clock edge,
wherein detecting bad symbols comprises:
using a voting scheme to determine whether the plurality of symbols is valid.
13. The method of claim 12 , wherein using the voting scheme comprises selecting a highest frequency symbol from the plurality of symbols to add to the sample sequence.
14. The method of claim 13 , wherein the highest frequency symbol is selected when a frequency of the highest frequency symbol satisfies a keep threshold.
15. A device comprising:
a multiphase clock having a plurality of clock edges, the plurality of clock edges being time staggered for the multiphase clock; and
a processing system configured to:
receive a multi-wire transitional coded signal,
sample, at each clock edge of the multiphase clock, the multi-wire transitional coded signal to obtain a sample sequence, and
output a symbol for each transition in the sample sequence to obtain an output device sequence,
wherein a number of clock edges is greater than the number of symbols.
16. The device of claim 15 , wherein the processing system is further configured to:
detect bad symbols in the sample sequence.
17. The device of claim 16 , wherein sampling the multi-wire transitional coded signal comprises:
obtaining a sequential set of matching symbols triggered by a clock edge of the multi-phase clock, and
wherein detecting bad symbols comprises:
dropping the sequential set of matching symbols when a number of the sequential set of matching symbols satisfies a drop threshold.
18. The device of claim 16 , wherein detecting bad symbols comprises:
dropping a sample when a length of time to sample the multi-wire transitional coded signal and obtain the sample satisfies a drop threshold.
19. The device of claim 16 , wherein sampling at a clock edge of the multiphase clock comprises:
sampling, by multiple samplers, the multi-wire transitional coded signal to obtain a plurality of symbols for the clock edge,
wherein detecting bad symbols comprises:
using a voting scheme to determine whether the plurality of symbols is valid.
20. The device of claim 19 , wherein using the voting scheme comprises selecting a highest frequency symbol from the plurality of symbols to add to the sample sequence.