Multi-level assurance trusted computing platform
View Patent ↗A multi-mode Trusted Computing Platform (TCP) comprising a Field Programmable Gate Array (FPGA) device that includes a Type-1-compliant root of trust (ROT), a memory containing a Type-1 security boot image and at least one lower-security boot image, and a memory containing a Type-1-associated operating system (OS) image and at least one lower-security-associated OS image. The TCP is configured to execute a multi-stage boot process that, depending on the presence of one or more valid external inputs, selects and initiates either a Type-1 TCP computing mode or a lower-assurance computing mode.
1. A multi-mode Trusted Computing Platform (TCP), comprising:
a. a Field Programmable Gate Array (FPGA) device that includes a Type-1-compliant root of trust (ROT);
b. memory containing a Type-1 security boot image and at least one lower-security boot image than the Type-1 security boot image; and
c. memory containing a Type-1-associated operating system (OS) image and at least one lower-security-associated OS image than the Type-1-associated OS image;
wherein the TCP is configured to execute a multi-stage boot process that, depending on presence of one or more valid external inputs, selects and initiates either a Type-1 TCP computing mode or a lower-assurance computing mode than the Type-1 TCP computing mode;
wherein the TCP is configured such that a set of input/output (I/O) devices and applications with which the TCP can interact depends upon the computing mode selected and initiated by the TCP; and
wherein the TCP is configured to have functionality and access that, when in Type-1 TCP computing mode, is restricted and controlled by the FPGA-based TCP (FTCP) per Type-1 protocol and is isolated from all non-Type-1 TCP computing mode functionality, applications, files systems, and devices.
2. The TCP of claim 1 , wherein the one or more valid external inputs include a portable device.
3. The TCP of claim 2 , wherein the portable device is a Crypto Ignition Key (CIK) device, Universal Serial Bus (USB) token, or Radio Frequency Identification (RFID) device.
4. The TCP of claim 1 , wherein the TCP is configured to be unable to access Type-1 TCP functionality and areas when in non-Type-1 TCP computing mode.
5. The TCP of claim 1 , wherein the TCP is configured to check for the presence of the one or more valid external inputs.
6. The TCP of claim 5 , wherein the FPGA is configured to boot a Type-1 compliant FPGA-based TCP (FTCP) upon a successful check for the presence of the one or more valid external inputs corresponding to Type-1 TCP computing mode.
7. The TCP of claim 6 , wherein the FPGA is configured to initiate booting of the FTCP with booting of a FPGA-based root of trust (FROT).
8. The TCP of claim 7 , further comprising a main processor, wherein the FTCP is configured to link the FROT to higher-level security means implemented on the main processor.
9. The TCP of claim 8 , wherein the higher-level security means comprise Trusted Platform Module or TrustZone.
10. The TCP of claim 8 , wherein the higher-level security means comprise a trusted kernel.
11. The TCP of claim 8 , wherein the higher-level security means comprise a hypervisor.
12. The TCP of claim 11 , wherein the FTCP is integrated into the hypervisor.
13. The TCP of claim 1 , wherein the FTCP is configured to surround and control all security-sensitive system elements.
14. The TCP of claim 13 , further comprising a main processor, wherein the FTCP is configured to treat the main processor as untrusted and to maintain hardware control over the main processor.
15. The TCP of claim 14 , wherein the FTCP is configured to perform hardware control that includes enable/disable control, power control, and/or data stream processing.
16. The TCP of claim 14 , wherein the FTCP is configured to perform hardware control that includes in-line data stream processing comprising processing, inspection, and encryption.
17. The TCP of claim 14 , wherein the FTCP is configured to process complex protocol stacks and perform authorization and control of data traffic.
18. The TCP of claim 14 , wherein the FTCP is configured to perform hardware control that includes encrypting and decrypting all main processor read/write memory access.
19. The TCP of claim 14 , wherein the FTCP is configured to control the main processor boot process.
20. The TCP of claim 19 , wherein the FTCP is configured to read, validate, decrypt, verify, and load onto the main processor a Type-1-associated OS image.
21. The TCP of claim 14 , wherein the FTCP is configured to read, validate, decrypt, and verify all main processor sub-processes and applications.
22. The TCP of claim 21 , wherein the FTCP is configured to link validation to higher-level security means implemented on the main processor.
23. The TCP of claim 14 , wherein the FTCP is configured to monitor main processor activity for anomalies.
24. The TCP of claim 14 , wherein the main processor includes one or more physically-integrated secure boot protections.