IP Library Granted Patent US 9,361,169
Granted Patent B2
US 9,361,169 · App. 14/173,101 · Granted Jun 7, 2016

Systems and methods for error correction in quantum computation

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Quick Facts
Patent No.
US 9,361,169
App. No.
14/173,101
Granted
Jun 7, 2016
Kind
B2
Abstract

The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.

Claims (31)

1. An analog computer for solving a computational problem, the analog computer comprising:

a quantum processor comprising:

a first set of qubits and a first set of coupling devices that provide communicative coupling between qubits in the first set of qubits, the first set of qubits and the first set of coupling devices representing a first instance of the computational problem programmed into the quantum processor;

a first set of replica qubits and a first set of replica coupling devices that provide communicative coupling between the first set of replica qubits, the first set of replica qubits and the first set of replica coupling devices representing a second instance of the computational problem programmed into the quantum processor, wherein for each qubit in the first set of qubits a corresponding replica qubit exists in the first set of replica qubits, and for each coupling device in the first set of coupling devices a replica coupling device exists in the first set of replica coupling devices; and

a second set of coupling devices, wherein each coupling device in the second set of coupling devices provides communicative coupling between a qubit in the first set of qubits and the corresponding replica qubit in the first set of replica qubits, the analog computer further comprising:

one or more readout devices operable to read out the state of one or more of the first set of qubits and the first set of replica qubits;

a qubit control system communicatively coupled to control one or more of the first set of qubits and the first set of replica qubits; and

a coupler control system communicatively coupled to control one or more of the first set of coupling devices, the first set of replica coupling devices, and the second set of coupling devices,

wherein the analog computer is selectively operable to perform quantum annealing on the first and the second instances of the computational problem at the same time to reduce the effects of decoherence and noise.

2. The analog computer of claim 1 wherein the quantum processor is a superconducting quantum processor, the qubits in the first set of qubits and the first set of replica qubits are superconducting qubits, and the coupling devices in the first set of coupling devices, the first set of replica coupling devices, and the second set of coupling devices are superconducting coupling devices.

3. The analog computer of claim 2 wherein the qubits are superconducting flux qubits.

4. The analog computer of claim 1 wherein at least some of the coupling devices of each of the first set of coupling devices, the first set of replica coupling devices, and the second set of coupling devices are operable to provide a respective diagonal coupling.

5. The analog computer of claim 1 , wherein the quantum processor further comprises:

a first interface that in use provides off-diagonal single qubit terms of the Hamiltonians of the first set of qubits and the first set of replica qubits;

a second interface that in use provides diagonal single qubit terms of the Hamiltonians of the first set of qubits and the first set of replica qubits; and

a third interface that in use provides diagonal two qubit terms of the Hamiltonians of the first set of qubits and the first set of replica qubits, wherein the diagonal two qubit terms are associated with the first set of coupling devices and the first set of replica coupling devices.

6. The analog computer of claim 1 wherein the quantum processor further comprises:

a second set of replica qubits and a second set of replica coupling devices that provide communicative coupling between the second set of replica qubits, the second set of replica qubits and the second set of replica coupling devices representing a third instance of the computational problem programmed into the quantum processor, wherein for each qubit in the first set of qubits a corresponding replica qubit exists in the second set of replica qubits, and for each coupling device in the first set of coupling devices a replica coupling device exists in the second set of replica coupling devices; and

a third set of coupling devices, wherein each coupling device in the third set of coupling devices provides communicative coupling between a qubit in the first set of qubits and the corresponding replica qubit in the second set of replica qubits;

one or more readout devices operable to read out the state of one or more of the second set of replica qubits;

a qubit control system communicatively coupled to control one or more of the second set of replica qubits; and

a coupler control system communicatively coupled to control one or more of the second set of replica coupling devices, and the third set of coupling devices,

wherein the analog computer is selectively operable to perform quantum annealing on the first, the second and the third instances of the computational problem at the same time to reduce the effects of decoherence and noise.

7. The analog computer of claim 1 wherein the first instance of the computational problem programmed into the quantum processor is different than the second instance of the computational problem programmed into the quantum processor, and the analog computer is selectively operable to realize a selected error correction code.

8. The analog computer of claim 7 wherein the selected error correction code is a majority voting scheme.

9. The analog computer of claim 1 wherein the strength of coupling of one or more of the second set of coupling devices is less than the strength of coupling of one or more of the first set of coupling devices and one or more of the first set of replica coupling devices.

10. The analog computer of claim 1 wherein the quantum processor further comprises:

a first physical layer, the first set of qubits and the first set of coupling devices arranged on the first physical layer; and

a second physical layer, the first set of replica qubits and the first set of replica coupling devices arranged on the second physical layer.

11. The analog computer of claim 1 wherein the readout devices are selectively operable to read out the state of one or more qubits in one of either the first set of qubits or the first set of replica qubits.

12. The analog computer of claim 1 wherein a readout device is selectively operable to read out the state of a respective qubit from both the first set of qubits and from the first set of replica qubits.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2025
From: PSPIB UNITAS INVESTMENTS II INC.
To: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
Reel/Frame 070470/0098 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 14, 2023
From: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
To: PSPIB UNITAS INVESTMENTS II INC., AS COLLATERAL AGENT
Reel/Frame 063340/0888 →
RELEASE OF SECURITY INTEREST Recorded Sep 20, 2022
From: PSPIB UNITAS INVESTMENTS II INC., IN ITS CAPACITY AS COLLATERAL AGENT
To: D-WAVE SYSTEMS INC.
Reel/Frame 061493/0694 →
SECURITY INTEREST Recorded Mar 3, 2022
From: D-WAVE SYSTEMS INC.
To: PSPIB UNITAS INVESTMENTS II INC.
Reel/Frame 059317/0871 →
SECURITY INTEREST Recorded Nov 29, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 051144/0499 →
SECURITY INTEREST Recorded Mar 22, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 048674/0188 →
RELEASE OF SECURITY INTEREST Recorded Apr 13, 2017
From: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 042252/0256 →
CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO. 8733763 PREVIOUSLY RECORDED AT REEL: 034841 FRAME: 0497. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Jan 30, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034862/0237 →
SECURITY INTEREST Recorded Jan 29, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034841/0497 →