Process methods for advanced interconnect patterning
View Patent ↗Methods for achieving advanced patterning of an interconnect dielectric material layer are provided in which the dimension, i.e., width, of an opening that is formed into a metallic hard mask layer is shrunk prior to extending the opening into the interconnect dielectric material layer. The shrinking of the dimension of the opening that is formed into the metallic hard mask layer can be achieved in the present application by forming at least a metallic hard mask spacer portion on a sidewall surface of each patterned metallic hard mask layer. The aforementioned basic principle can be applied to forming a line opening, a via opening and/or a combined via and line opening within an interconnect dielectric material layer, wherein each of the openings (line, via and/or via and line) has a reduced dimension as compared to that obtainable utilizing conventional lithography.
1. A method of forming an interconnect structure comprising:
providing a structure including, from bottom to top, an interconnect dielectric material layer, a dielectric hard mask layer, and a metallic hard mask layer;
patterning said metallic hard mask layer to provide metallic hard mask portions on said dielectric hard mask layer, wherein adjacent metallic hard mask portions are spaced apart by a first opening having a first width;
reducing said first width of said first opening to provide a second opening having a second width, wherein said reducing said first width of said first opening to provide said second opening having said second width comprises forming a metallic hard mask structure comprising at least a metallic hard mask spacer portion on a sidewall surface of each metallic hard mask portion; and
extending said second opening having said second width entirely through said dielectric hard mask layer and at least partially through the interconnect dielectric material layer to provide an interconnect dielectric material structure having said second opening with said second width.
2. The method of claim 1 , wherein said metallic hard mask structure further comprises forming a metallic hard mask cap portion on a topmost surface of each metallic hard mask portion and in direct contact with said metallic hard mask spacer portion, wherein said metallic hard mask cap portion and said metallic hard mask spacer portion comprise a same metallic hard mask material and are of unitary construction.
3. The method of claim 1 , further comprising forming a diffusion barrier liner and a conductive structure in said second opening of said interconnect dielectric material structure.
4. The method of claim 3 , wherein said forming said diffusion barrier liner and said conductive structure comprises:
depositing a diffusion barrier layer lining at least said second opening of said interconnect dielectric material structure;
depositing a conductive material on said diffusion barrier layer; and
planarizing to a topmost surface of said interconnect dielectric material structure.
5. The method of claim 4 , wherein said planarizing removes portions of said conductive material, portions of said diffusion barrier layer, said metallic hard mask portions and said dielectric hard mask layer from said topmost surface of said interconnect dielectric material structure.
6. The method of claim 1 , wherein said second opening is a line opening, and said second width is from 5 nm to 30 nm.
7. A method of forming an interconnect structure comprising:
providing a structure including, from bottom to top, an interconnect dielectric material layer, a dielectric hard mask layer, and a metallic hard mask layer;
patterning said metallic hard mask layer to provide metallic hard mask portions on said dielectric hard mask layer, wherein adjacent metallic hard mask portions are spaced apart by a first opening having a first width;
forming a block mask on a topmost surface of each metallic hard mask portion but not covering said first opening;
reducing said first width of said first opening to provide a second opening having a second width, wherein said reducing said first width of said first opening to provide said second opening having said second width comprises forming a metallic hard mask structure comprising at least a metallic hard mask spacer portion on a sidewall surface of each metallic hard mask portion; and
extending said second opening having said second width entirely through said dielectric hard mask layer and at least partially through the interconnect dielectric material layer to provide an interconnect dielectric material structure having said second opening with said second width.
8. The method of claim 7 further comprising removing said block mask and then forming a diffusion barrier liner and a conductive structure in said second opening of said interconnect dielectric material structure.
9. The method of claim 8 , wherein said forming said diffusion barrier liner and said conductive structure comprises:
depositing a diffusion barrier layer lining at least said second opening of said interconnect dielectric material structure;
depositing a conductive material on said diffusion barrier layer; and
planarizing to a topmost surface of said interconnect dielectric material structure.
10. The method of claim 8 , wherein said planarizing removes portions of said conductive material, portions of said diffusion barrier layer, said metallic hard mask portions and said dielectric hard mask layer from said topmost surface of said interconnect dielectric material structure.
11. The method of claim 7 , wherein said second opening is a via opening, and said second width is from 5 nm to 30 nm.
12. A method of forming an interconnect structure comprising:
providing a structure including, from bottom to top, an interconnect dielectric material layer, a dielectric hard mask layer, and a metallic hard mask layer;
patterning said metallic hard mask layer to provide metallic hard mask portions on said dielectric hard mask layer, wherein adjacent metallic hard mask portions are spaced apart by a line opening having a first width;
forming a block mask on a topmost surface of each metallic hard mask portion but not covering said line opening;
reducing said first width of said line opening to provide a via opening having a second width by forming a metallic hard mask spacer portion on a sidewall surface of each metallic hard mask portion;
extending said via opening having said second width entirely through said dielectric hard mask layer and at least partially through the interconnect dielectric material layer to provide an interconnect dielectric material structure having said via opening with said second width;
removing the metallic hard mask spacer portion from said sidewall surface of each metallic hard mask portion to restore said line opening having said first width between said adjacent metallic hard mask portions; and
extending said line opening having said first width entirely through said dielectric hard mask layer and partially through the interconnect dielectric material structure, wherein said line opening having the first width is located in an upper portion of said interconnect dielectric material structure and said via opening of the second width is located in a lower portion of the interconnect dielectric material structure.
13. The method of claim 12 , wherein said metallic hard mask spacer portion comprises a metallic hard mask material having a different etch rate than said metallic hard mask layer.
14. The method of claim 13 , wherein said removing the metallic hard mask spacer portion from said sidewall surface of each metallic hard mask portion comprises a selective etching process.
15. The method of claim 12 further comprising removing said block mask and then forming a diffusion barrier liner and a conductive structure in said via opening and said line opening of said interconnect dielectric material structure.
16. The method of claim 15 , wherein said forming said diffusion barrier liner and said conductive structure comprises:
depositing a diffusion barrier layer lining at said via opening and said line opening of said interconnect dielectric material structure;
depositing a conductive material on said diffusion barrier layer; and
planarizing to a topmost surface of said interconnect dielectric material structure.
17. The method of claim 16 , wherein said planarizing removes portions of said conductive material, portions of said diffusion barrier layer, said metallic hard mask portions and said dielectric hard mask layer from said topmost surface of said interconnect dielectric material structure.