Communication apparatus and communication method
View Patent ↗A wireless communication apparatus and a wireless communication method wherein even when the permissible delay amount of data is small, the permissible delay thereof can be satisfied. A data type determining part determines whether the delay of transport data or control information should be allowed or not. A pilot signal insertion control part decides, based on pilot insertion interval information and allowable delay information, that a pilot signal is placed adjacently to data that is not allowed to delay. A multiplexing part multiplexes encoded and modulated transport data with the pilot signal generated by a pilot signal generating part in such a manner that realizes the placement decided by the pilot signal insertion control part.
1. An integrated circuit for controlling a process comprising:
mapping a pilot signal for control information or a pilot signal for data to a symbol; and
transmitting the pilot signal that is mapped,
wherein the pilot signal is mapped such that a number of symbols to which the pilot signal for the control information is mapped are greater than a number of symbols to which the pilot signal for the data is mapped.
2. The integrated circuit according to claim 1 , wherein the pilot signal is mapped such that a number of symbols, to which the pilot signal for the control information is mapped, per a predefined time, are greater than a number of symbols, to which the pilot signal for the data is mapped, per the predefined time.
3. The integrated circuit according to claim 1 , wherein the pilot signal is mapped such that the pilot signal for the control information is denser than the pilot signal for the data.
4. The integrated circuit according to claim 1 , wherein the pilot signal for the control information is mapped to all subcarriers.
5. The integrated circuit according to claim 1 , wherein the pilot signal for the control information is mapped to a part of all subcarriers.
6. The integrated circuit according to claim 1 , wherein the pilot signal for the control information is mapped close to a symbol, to which the control information is mapped.
7. The integrated circuit according to claim 1 , wherein the pilot signal for the control information is mapped just after a symbol, to which the control information is mapped.
8. The integrated circuit according to claim 1 , wherein the pilot signal for the control information is mapped just before a symbol, to which the control information is mapped.
9. The integrated circuit according to claim 1 , wherein the pilot signal for the control information is mapped between symbols, to which the control information is mapped.
10. The integrated circuit according to claim 1 , wherein the control information is an ACK/NACK or a channel quality indicator.
11. The integrated circuit according to claim 1 , wherein the control information is scheduling information.
12. The integrated circuit according to claim 1 , wherein the control information allows little delay.
13. The integrated circuit according to claim 1 , wherein the pilot signal is used for demodulation of the control information or the data.
14. The integrated circuit according to claim 1 , wherein the pilot signal is used for channel estimation.
15. The integrated circuit according to claim 1 , wherein the pilot signal is transmitted by multiplexing with the control information or the data.
16. The integrated circuit according to claim 1 , wherein the pilot signal is transmitted in a single carrier.
17. The integrated circuit according to claim 1 , wherein the pilot signal is transmitted by amplifying transmission power thereof.
18. An integrated circuit for controlling a process comprising:
receiving at least one of a pilot signal for control information and a pilot signal for data to a symbol; and
demodulating at least one of the control information and the data using the pilot signal,
wherein the pilot signal is mapped such that a number of symbols to which the pilot signal for the control information is mapped are greater than a number of symbols to which the pilot signal for the data is mapped.
19. The integrated circuit according to claim 18 , the process further comprises performing a channel estimation using the pilot signal, wherein at least of the control information and the data is demodulated based on the channel estimation.
20. The integrated circuit according to claim 18 , wherein the pilot signal is mapped such that a number of symbols, to which the pilot signal for the control information is mapped, per a predefined time, are greater than a number of symbols, to which the pilot signal for the data is mapped, per the predefined time.
21. The integrated circuit according to claim 18 , wherein the pilot signal is mapped such that the pilot signal for the control information is denser than the pilot signal for the data.
22. The integrated circuit according to claim 18 , wherein the pilot signal for the control information is mapped to all subcarriers.
23. The integrated circuit according to claim 18 , wherein the pilot signal for the control information is mapped to a part of all subcarriers.
24. The integrated circuit according to claim 18 , wherein the pilot signal for the control information is mapped close to a symbol, to which the control information is mapped.
25. The integrated circuit according to claim 18 , wherein the pilot signal for the control information is mapped just after a symbol, to which the control information is mapped.
26. The integrated circuit according to claim 18 , wherein the pilot signal for the control information is mapped just before a symbol, to which the control information is mapped.
27. The integrated circuit according to claim 18 , wherein the pilot signal for the control information is mapped between symbols, to which the control information is mapped.
28. The integrated circuit according to claim 18 , wherein the control information is an ACK/NACK or a channel quality indicator.
29. The integrated circuit according to claim 18 , wherein the control information is scheduling information.
30. The integrated circuit according to claim 18 , wherein the control information allows little delay.