IP Library Granted Patent US 9,069,928
Granted Patent B2
US 9,069,928 · App. 14/175,731 · Granted Jun 30, 2015

Analog processor comprising quantum devices

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Quick Facts
Patent No.
US 9,069,928
App. No.
14/175,731
Granted
Jun 30, 2015
Kind
B2
Abstract

Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.

Claims (57)

1. A computational system, comprising:

at least one processor;

at least one nontransitory processor-readable medium that stores at least one of processor-executable instructions or data, which when executed by the at lease one processor produces a graphical user interface for obtaining a solution to a computational problem, the graphical user interface comprising:

(A) a first display field for indicating when a digital signal embodied on a carrier wave comprising a respective value for each node in a plurality of nodes has been received;

wherein the plurality of nodes are at least two nodes in a lattice of nodes in a quantum processor, and wherein each node in the lattice of nodes is a quantum device; and

wherein a value of at least one node in the plurality of nodes individually or collectively represents the solution to the computational problem that has been solved by evolving the quantum processor at a time after a graph representing the computational problem has been mapped onto at least a portion of the lattice; and

(B) a second display field for displaying the solution to the computational problem.

2. The computational system of claim 1 , wherein the computational problem is selected from the group consisting of a problem having a complexity of P, a problem having a complexity of NP, a problem having a complexity of NP-Hard, and a problem having a complexity of NP-Complete.

3. The computational system of claim 1 , wherein the plurality of nodes comprises at least 16 nodes.

4. The computational system of claim 1 , wherein the respective value of a node in the plurality of nodes is a binary value.

5. The computational system of claim 1 , wherein the graph is selected from the group consisting of K 5 , K 3,3 , an expansion of K 5 , and an expansion of K 3,3 .

6. A computational system, comprising:

at least one processor;

at least one nontransitory processor-readable medium that stores at least one of processor-executable instructions or data, which when executed by the at lease one processor produces a graphical user interface for obtaining a solution to a computational problem, the graphical user interface comprising:

(A) a first display field for indicating when a digital signal embodied on a carrier wave comprising an answer to the computational problem has been received;

wherein the answer to the computational problem was determined by evaluating a value of at least one node in a plurality of nodes;

wherein the plurality of nodes are at least two nodes in a lattice of nodes in a quantum processor, and wherein each node in the lattice of nodes is a quantum device; and

wherein the value of at least one node in the plurality of nodes is determined after evolving the quantum processor at a time after a graph representing the computational problem has been mapped onto at least a portion of the lattice; and

(B) a second display field for displaying the solution to the computational problem.

7. The computational system of claim 6 , wherein the carrier wave is received from a remote computer.

8. A computational system, comprising:

at least one processor;

at least one nontransitory processor-readable medium that stores at least one of processor-executable instructions or data, which when executed by the at lease one processor produces a graphical user interface, the graphical user interface comprising:

(A) a first display field for indicating when a digital signal embodied on a carrier wave comprising the computational problem to be solved by a quantum processor has been generated;

wherein the quantum processor comprises a lattice of quantum devices;

wherein the computational problem to be solved comprises a plurality of nodes and, for each respective node in the plurality of nodes, an initial value for the respective node and a corresponding coupling constant between the respective node and another node in the plurality of nodes; and

wherein the computational problem to be solved is configured so that it can be mapped to the lattice of the quantum processor; and

(B) a second display field for displaying the solution to the computational problem after it has been received.

9. The computational system of claim 8 , wherein the digital signal is sent to a remote computer that is in communication with the quantum processor.

10. The computational system of claim 8 , wherein the digital signal is sent directly to the quantum processor.

11. The computational system of claim 8 , wherein the solution to the computational problem is received from a remote computer that is in communication with the quantum processor.

12. The computational system of claim 8 , wherein the solution to the computational problem is received directly from the quantum processor.

13. The computational system of claim 8 , wherein the computational problem to be solved is represented in said digital signal as a graph.

14. A computer system for determining a result of a computational problem, the computer system comprising:

a local computer;

a remote computer; and

an analog processor; wherein

the local computer comprises a central processing unit and a memory, coupled to the central processing unit, the memory storing:

a user interface module comprising instructions for defining the computational problem;

a mapper module comprising instructions for generating a mapping of the computational problem; and

a transmit module comprising instructions for sending the mapping to the remote computer;

the remote computer comprises a central processing unit and a memory, coupled to the central processing unit, the memory storing:

a receive module comprising instructions for receiving the mapping from the local computer;

an analog processor interface module comprising instructions for transmitting the mapping to the analog processor; and

the analog processor comprises a plurality of quantum devices and a plurality of coupling devices, and wherein the mapping includes initialization values for at least one of the quantum devices in the plurality of quantum devices and initialization values for at least one of the coupling devices in the plurality of coupling devices, wherein a coupling device in the plurality of coupling devices couples a corresponding respective quantum device in the plurality of quantum devices to at least one of a nearest neighbor of the respective quantum device and a next-nearest neighbor of the respective quantum device.

15. A computer system for determining a result of a computational problem, the computer system comprising:

a local computer;

a remote computer; and

an analog processor; wherein

the local computer comprises a central processing unit and a memory, coupled to the central processing unit, the memory storing:

a user interface module comprising instructions for defining the computational problem; and

a transmit module comprising instructions for sending the computational problem to the remote computer;

the remote computer comprises a central processing unit and a memory, coupled to the central processing unit, the memory storing:

a receive module comprising instructions for receiving the computational problem from the local computer;

a mapper module comprising instructions for generating a mapping of the computational problem; and

an analog processor interface module comprising instructions for transmitting the mapping to the analog processor; and

the analog processor comprises a plurality of quantum devices and a plurality of coupling devices, and wherein the mapping includes initialization values for at least one of the quantum devices in the plurality of quantum devices and initialization values for at least one of the coupling devices in the plurality of coupling devices, wherein a coupling device in the plurality of coupling devices couples a corresponding respective quantum device in the plurality of quantum devices to at least one of a nearest neighbor of the respective quantum device and a next-nearest neighbor of the respective quantum device.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2025
From: PSPIB UNITAS INVESTMENTS II INC.
To: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
Reel/Frame 070470/0098 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 14, 2023
From: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
To: PSPIB UNITAS INVESTMENTS II INC., AS COLLATERAL AGENT
Reel/Frame 063340/0888 →
RELEASE OF SECURITY INTEREST Recorded Sep 20, 2022
From: PSPIB UNITAS INVESTMENTS II INC., IN ITS CAPACITY AS COLLATERAL AGENT
To: D-WAVE SYSTEMS INC.
Reel/Frame 061493/0694 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2022
From: BERKLEY, ANDREW J.; VAN DEN BRINK, ALEC MAASSEN; LOVE, PETER; AMIN, MOHAMMAD H.S.; ROSE, GEORDIE; GRANT, DAVID; STEININGER, MILES F.H.; BUNYK, PAUL
To: D-WAVE SYSTEMS INC.
Reel/Frame 060336/0400 →
CONTINUATION Recorded Jun 28, 2022
From: D-WAVE SYSTEMS INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 060448/0485 →
SECURITY INTEREST Recorded Mar 3, 2022
From: D-WAVE SYSTEMS INC.
To: PSPIB UNITAS INVESTMENTS II INC.
Reel/Frame 059317/0871 →
SECURITY INTEREST Recorded Nov 29, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 051144/0499 →
SECURITY INTEREST Recorded Mar 22, 2019
From: D-WAVE SYSTEMS INC.
To: BDC CAPITAL INC.
Reel/Frame 048674/0188 →
RELEASE OF SECURITY INTEREST Recorded Apr 13, 2017
From: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 042252/0256 →
CORRECTIVE ASSIGNMENT TO REMOVE APPL. NO. 8733763 PREVIOUSLY RECORDED AT REEL: 034841 FRAME: 0497. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Jan 30, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034862/0237 →
SECURITY INTEREST Recorded Jan 29, 2015
From: D-WAVE SYSTEMS INC.
To: VENTURE LENDING & LEASING VI, INC.; VENTURE LENDING & LEASING VII, INC.
Reel/Frame 034841/0497 →