Check operation dispersed storage network frame
View Patent ↗A method begins by a processing module generating a payload section of a dispersed storage network (DSN) frame regarding a check request operation by generating one or more slice name fields of the payload section to include one or more slice names corresponding to one or more encoded data slices and generating a transaction number field of the payload section to include a transaction number corresponding to the check request operation. The method continues with the processing module generating a protocol header of the DSN frame by generating a payload length field of the protocol header to include a payload length that represents a length of the payload section and generating remaining fields of the protocol header.
1. A method for executing a check request operation by a computing device, the method comprises:
generating a set of check request frames, wherein each check request frame of the set of check request frames is generated by:
generating a unique payload section to include:
one or more slice name fields of the unique payload section to include one or more unique slice names corresponding to one or more unique dispersed storage error encoded data slices; and
a common transaction number field of the unique payload section to include a common transaction number corresponding to the check request operation; and
generating a protocol header to include:
a payload length field, which includes a payload length that represents a length of the unique payload section; and
one or more remaining fields of the protocol header; and
outputting the set of check request frames to a set of storage units of a dispersed storage network.
2. The method of claim 1 further comprises:
ordering a check frame request of the set of check frame requests in an order of the protocol header, the common transaction number field, and the one or more slice name fields.
3. The method of claim 1 , wherein generating the one or more remaining fields of the protocol header comprises at least one of:
generating an operation code field to indicate the check request operation;
generating a protocol class field to indicate a protocol class for the check request operation; or
generating a protocol class version field for the check request operation.
4. The method of claim 1 further comprises:
generating the common transaction number by:
obtaining a clock value;
multiplying the clock value by a predetermined multiplier to produce an expanded clock value; and
summing the expanded clock value and a random number to produce a value, wherein a number of digits of the random number is substantially the same as a number of digits of the predetermined multiplier.
5. The method of claim 1 further comprises:
determining a length of the common transaction number;
determining a length for each of the one or more slices names;
determining a number of slice names of the one or more slices names; and
generating the payload length for the payload length field based on the length of the common transaction number, the length for each of the one or more slices names, and the number of slice names of the one or more slices names.
6. A computer comprises:
an interface;
a memory; and
a processor operably coupled to the interface and to the memory, wherein the processor is operable to:
generate a set of check request frames, wherein each check request frame of the set of check request frames is generated by:
generating a unique payload section to include:
one or more slice name fields of the unique payload section to include one or more unique slice names corresponding to one or more unique dispersed storage error encoded data slices; and
a common transaction number field of the unique payload section to include a common transaction number corresponding to a check request operation; and
generate a protocol header to include:
a payload length field, which includes a payload length that represents a length of the unique payload section; and
one or more remaining fields of the protocol header; and
output, via the interface, the set of check request frames to a set of storage units of a dispersed storage network.
7. The computer of claim 6 , wherein the processor is further operable to:
order a check frame request of the set of check frame requests in an order of the protocol header, the common transaction number field, and the one or more slice name fields.
8. The computer of claim 6 , wherein the processor is further operable to generate the one or more remaining fields of the protocol header by at least one of:
generating an operation code field to indicate the check request operation;
generating a protocol class field to indicate a protocol class for the check request operation; or
generating a protocol class version field for the check request operation.
9. The computer of claim 6 , wherein the processor is further operable to:
generate the common transaction number by:
obtaining a clock value;
multiplying the clock value by a predetermined multiplier to produce an expanded clock value; and
summing the expanded clock value and a random number to produce a value, wherein a number of digits of the random number is substantially the same as a number of digits of the predetermined multiplier.
10. The computer of claim 6 , wherein the processor is further operable to:
determine a length of the common transaction number;
determine a length for each of the one or more slices names;
determine a number of slice names of the one or more slices names; and
generate the payload length for the payload length field based on the length of the common transaction number, the length for each of the one or more slices names, and the number of slice names of the one or more slices names.
11. The computer of claim 6 , wherein the processor comprises one or more of:
a microprocessor, a micro-controller, a digital signal processor, a microcomputer, a central processing unit, a field programmable gate array, a programmable logic device, a state machine, logic circuitry, analog circuitry, digital circuitry, and a device that manipulates signals based on at least one of hard coding and operational instructions.
12. A computer readable memory device comprises:
a first memory section that stores operational instructions that, when executed by a computing device, causes the computing device to generate a set of check request frames, wherein each check request frame of the set of check request frames is generated by:
generating a unique payload section to include:
one or more slice name fields of the unique payload section to include one or more unique slice names corresponding to one or more unique dispersed storage error encoded data slices; and
a common transaction number field of the unique payload section to include a common transaction number corresponding to a check request operation; and
generate a protocol header to include:
a payload length field, which includes a payload length that represents a length of the unique payload section; and
one or more remaining fields of the protocol header; and
a second memory section that stores operational instructions that, when executed by the computing device, causes the computing device to output, via an interface of the computing device, the set of check request frames to a set of storage units of a dispersed storage network.
13. The computer readable memory device of claim 12 , wherein the first memory section further stores operational instructions that, when executed by the computing device, causes the computing device to:
order a check frame request of the set of check frame requests in an order of the protocol header, the common transaction number field, and the one or more slice name fields.
14. The computer readable memory device of claim 12 , wherein the first memory section further stores operational instructions that, when executed by the computing device, causes the computing device to generate the one or more remaining fields of the protocol header by at least one of:
generating an operation code field to indicate the check request operation;
generating a protocol class field to indicate a protocol class for the check request operation; or
generating a protocol class version field for the check request operation.
15. The computer readable memory device of claim 12 , wherein the first memory section further stores operational instructions that, when executed by the computing device, causes the computing device to:
generate the common transaction number by:
obtaining a clock value;
multiplying the clock value by a predetermined multiplier to produce an expanded clock value; and
summing the expanded clock value and a random number to produce a value, wherein a number of digits of the random number is substantially the same as a number of digits of the predetermined multiplier.
16. The computer readable memory device of claim 12 , wherein the first memory section further stores operational instructions that, when executed by the computing device, causes the computing device to:
determine a length of the common transaction number;
determine a length for each of the one or more slices names;
determine a number of slice names of the one or more slices names; and
generate the payload length for the payload length field based on the length of the common transaction number, the length for each of the one or more slices names, and the number of slice names of the one or more slices names.