3D bond and assembly process for severely bowed interposer die
View Patent ↗An interposer structure containing a first set of solder balls is placed in proximity to a vacuum distribution plate which has a planar contact surface and a plurality of openings located therein. A vacuum is then applied through the openings within the vacuum distribution plate such that the first set of solder balls are suspended within the plurality of openings and the interposer structure conforms to the planar contact surface of the vacuum distribution plate. A semiconductor chip containing a second set of solder balls is tacked to a surface of the interposer structure. A substrate is then brought into contact with a surface of the interposer structure containing the first set of solder balls, and then a solder reflow and underfill processes can be performed. Warping of the interposer structure is substantially eliminated using the vacuum distribution plate mentioned above.
1. A bonding method comprising:
inserting an interposer structure into a vacuum distribution plate, wherein said vacuum distribution plate has a planar contact surface;
applying a vacuum to a first assembly of said interposer structure and said vacuum distribution plate, wherein said vacuum applies a force to said interposer structure so that said interposer structure is conformed to said planar contact surface of said vacuum distribution plate, wherein conforming said interposer structure to said planar contact surface of said vacuum distribution plate removes a curvature from said interposer structure;
tacking a semiconductor chip to a surface of said interposer structure that is opposite a surface of said interposer structure that is in contact with said planar contact surface of said vacuum distribution plate;
contacting a second assembly of said interposer structure and said semiconductor chip to a substrate; and
applying a furnace reflow process to said second assembly to bond said second assembly to said substrate.
2. The bonding method of claim 1 , wherein said interposer structure includes a first set of solder balls and said semiconductor chip includes a second set of solder balls.
3. The bonding method of claim 2 , wherein said interposer structure comprises a semiconductor base material and interconnect circuitry.
4. The bonding method of claim 3 , wherein said interposer structure comprises logic devices, memory devices, devices for voltage regulation, or a combination thereof.
5. The bonding method of claim 2 , wherein said vacuum distribution plate has a series of openings separated by a distance corresponding to a distance separating adjacent solder balls in said first set of solder balls.
6. The bonding method of claim 1 , wherein said vacuum distribution plate comprises a material having first coefficient of thermal expansion and said interposer structure comprises an interposer component having a second coefficient of thermal expansion, wherein said first coefficient of thermal expansion substantially equals the second coefficient of thermal expansion.
7. The bonding method of claim 6 , wherein said vacuum distribution plate is composed of a semiconductor or dielectric material having openings formed by pattern and etch processing.
8. The bonding method of claim 5 , wherein said inserting said interposer structure into said vacuum distribution plate comprises positioning said first set of solder balls within said series of openings that are present in said vacuum distribution plate.
9. The bonding method of claim 5 , wherein said applying said vacuum to said first assembly of said interposer structure and said vacuum distribution plate comprises pulling said vacuum through said openings in said vacuum distribution plate, wherein said gauge pressure may range from −60 kPa to −90 kPa.
10. The bonding method of claim 5 , wherein said curvature of said interposer structure ranges from 500 μm to 1.5 mm, wherein a thickness for said interposer structure ranges from 30 μm to 50 μm.
11. The bonding method of claim 5 , wherein said vacuum is maintained during said tacking of said semiconductor chip to said surface of said interposer structure that is opposite said surface of said interposer structure that is in contact with said planar contact surface of said vacuum distribution plate.
12. The bonding method of claim 1 , wherein after tacking said semiconductor chip to said surface of said interposer structure, said interposer structure is substantially planar.
13. The bonding method of claim 5 , wherein said tacking of said semiconductor chip comprises applying a pressure to said second assembly of said interposer structure and said semiconductor chip, and thermal annealing said second assembly of said interposer structure and said semiconductor chip to provide a diffusion bonded connection between said second set of solder balls of said semiconductor chip and metal bond pads of said interposer structure.
14. The bonding method of claim 13 , wherein said thermal annealing is performed at a temperature ranging from 200° C. to 215° C.
15. The bonding method of claim 5 , wherein said furnace reflow process is performed at a temperature ranging from 218° C. to 260° C.
16. The bonding method of claim 1 , further comprising applying a weighted force to said surface of said semiconductor chip opposite a surface of said semiconductor chip that said second set of solder balls are present on between said tacking and said contacting steps.
17. The bonding method of claim 1 , wherein said furnace reflow process that is applied to said second assembly forms an intermetallic bond between said first set of solder balls and said substrate.
18. The bonding method of claim 1 , wherein said substrate is a laminated polymeric structure with metal vias and lines present therein.
19. The bonding method of claim 5 , further comprising an underfill process applied to said second assembly that is bonded to said substrate.