Granted Patent B2

US 9,264,074 · App. 14/177,707 · Granted Feb 16, 2016

Abstract

Claims (39)

1. A node comprising:

a non-transitory computer readable medium storing a sequence of instructions; and

a processor operable to execute the sequence of instructions to encode or decode data according to a first (low-density parity-check) LDPC parity check matrix, the first LDPC parity check matrix is a 7×46 matrix comprising:

a) a systematic portion having a plurality of systematic elements having a value, the value of each systematic element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to the systematic element, the systematic portion comprising a 7×39 matrix, the identity submatrix corresponding to each systematic element comprising a 100×100 identity matrix; and

b) a parity portion having a plurality of parity elements having a value, the value of each parity element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to the parity element, the parity portion comprising a 7×7 matrix, the identity submatrix corresponding to each parity element comprising a 100×100 identity matrix.

2. The node of claim 1 , wherein the processor is operable to execute the sequence of instructions to encode or decode data according to a second LDPC parity check matrix, the second LDPC parity check matrix comprising a permutation of the rows or columns of the first LDPC parity check matrix.

3. The node of claim 1 , wherein the processor is operable to execute the sequence of instructions to encode or decode data according to a second LDPC parity check matrix, the second LDPC parity check matrix comprising the first LDPC parity check matrix modified such that non-negative elements, H, of the first LDPC parity check matrix are replaced by (H+X)mod P, wherein X is greater than or equal to zero, and P is a parallelism of a code embodied by the first LDPC parity check matrix.

4. A node comprising:

a non-transitory computer readable medium storing a sequence of instructions; and

a processor operable to execute the sequence of instructions to encode or decode data according to a first (low-density parity-check) LDPC parity check matrix, the first LDPC parity check matrix comprising:

a) a systematic portion having a plurality of systematic elements having a value, the value of each systematic element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to the systematic element; and

b) a parity portion having a plurality of parity elements having a value, the value of each parity element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to the parity element,

wherein the systematic portion comprises a 5×41 matrix and the parity portion comprises a 5×5 matrix.

5. The node of claim 4 , wherein the processor is operable to execute the sequence of instructions to encode or decode data according to a second LDPC parity check matrix, the second LDPC parity check matrix comprising a permutation of the rows or columns of the first LDPC parity check matrix.

6. The node of claim 4 , wherein the processor is operable to execute the sequence of instructions to encode or decode data according to a second LDPC parity check matrix, the second LDPC parity check matrix comprising the first LDPC parity check matrix modified such that non-negative elements, H, of the first LDPC parity check matrix are replaced by (H+X)mod P, wherein X is greater than or equal to zero, and P is a parallelism of a code embodied by the first LDPC parity check matrix.

7. A node comprising:

a non-transitory computer readable medium storing a sequence of instructions; and

a processor operable to execute the sequence of instructions to encode or decode data according to a first (low-density parity-check) LDPC parity check matrix, the first LDPC parity check matrix comprising:

a) a systematic portion having a plurality of systematic elements having a value, the value of each systematic element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to the systematic element; and

b) a parity portion having a plurality of parity elements having a value, the value of each parity element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to the parity element,

wherein the systematic portion comprises a 6×34 matrix and the parity portion comprises a 6×6 matrix.

8. The node of claim 7 , wherein the processor is operable to execute the sequence of instructions to encode or decode data according to a second LDPC parity check matrix, the second LDPC parity check matrix comprising a permutation of the rows or columns of the first LDPC parity check matrix.

9. The node of claim 7 , wherein the processor is operable to execute the sequence of instructions to encode or decode data according to a second LDPC parity check matrix, the second LDPC parity check matrix comprising the first LDPC parity check matrix modified such that non-negative elements, H, of the first LDPC parity check matrix are replaced by (H+X)mod P, wherein X is greater than or equal to zero, and P is a parallelism of a code embodied by the first LDPC parity check matrix.

10. A node comprising:

a non-transitory computer readable medium storing a sequence of instructions; and

a processor operable to execute the sequence of instructions to encode or decode data according to a first (low-density parity-check) LDPC parity check matrix, the first LDPC parity check matrix comprising:

a) a systematic portion having a plurality of systematic elements having a value, the value of each systematic element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to the systematic element; and

b) a parity portion having a plurality of parity elements having a value, the value of each parity element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to the parity element,

wherein the systematic portion comprises a 5×43 matrix and the parity portion comprises a 5×5 matrix.

11. The node of claim 10 , wherein the processor is operable to execute the sequence of instructions to encode or decode data according to a second LDPC parity check matrix, the second LDPC parity check matrix comprising a permutation of the rows or columns of the first LDPC parity check matrix.

12. The node of claim 10 , wherein the processor is operable to execute the sequence of instructions to encode or decode data according to a second LDPC parity check matrix, the second LDPC parity check matrix comprising the first LDPC parity check matrix modified such that non-negative elements, H, of the first LDPC parity check matrix are replaced by (H+X)mod P, wherein X is greater than or equal to zero, and P is a parallelism of a code embodied by the first LDPC parity check matrix.

13. The node of claim 1 , wherein the encoded data is communicated between one or more other nodes.

14. The node of claim 1 , wherein the encoded data is communicated as packet according to a Media over Coax Alliance (MoCA) specification.

15. The node of claim 4 , wherein the encoded data is communicated between one or more other nodes.

16. The node of claim 4 , wherein the encoded data is communicated as packet according to a Media over Coax Alliance (MoCA) specification.

17. The node of claim 7 , wherein the encoded data is communicated between one or more other nodes.

18. The node of claim 7 , wherein the encoded data is communicated as packet according to a Media over Coax Alliance (MoCA) specification.

19. The node of claim 10 , wherein the encoded data is communicated between one or more other nodes.

20. The node of claim 10 , wherein the encoded data is communicated as packet according to a Media over Coax Alliance (MoCA) specification.

Assignments (10)