IP Library Granted Patent US 9,142,528
Granted Patent B2
US 9,142,528 · App. 14/179,263 · Granted Sep 22, 2015

Semiconductor device with an interlocking structure

Inventors: Keat Chuan Ng (Penang, MY); Kiam Soon Ong (Penang, MY); Kheng Leng Tan (Penang, MY)
Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
H01L24/70H01L33/62
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Quick Facts
Patent No.
US 9,142,528
App. No.
14/179,263
Granted
Sep 22, 2015
Kind
B2
Abstract

In one embodiment, a semiconductor device having a die attach pad, a semiconductor die and an adhesive material is disclosed. The adhesive material may be configured to adjoin the semiconductor die and the die attach pad. The die attach pad may be sandwiched between the semiconductor die and the die attach pad. In another embodiment, a device having a semiconductor die, a die attach glue and a die attach pad is disclosed. The device may comprise an interlock structure formed integrally with the die attach pad. In yet another embodiment, a light-emitting device comprising an interlock structure is disclosed.

Claims (40)

1. A semiconductor device, comprising:

a die attach pad;

a major surface of the die attach pad;

a semiconductor die mounted on the major surface;

an adhesive material configured to adjoin the semiconductor die and the die attach pad;

an encapsulant covering the die attach pad, the adhesive material and the semiconductor die; and

an interlock structure sandwiched between the semiconductor die and the major surface of the die attach pad,

wherein the interlock structure is an integral portion of the die attach pad and the interlock structure engages the adhesive material so as to interlock the die attach pad and the adhesive material.

2. The semiconductor device of claim 1 , wherein the adhesive material is formed between the semiconductor die and the die attach pad.

3. The semiconductor device of claim 1 , wherein the interlock structure is a portion of the die attach pad protruded from the major surface of the die attach pad.

4. The semiconductor device of claim 1 , wherein the interlock structure comprises a flange portion and a neck portion, wherein the neck portion adjoins the flange portion and the die attach pad.

5. The semiconductor device of claim 4 , wherein the flange portion has a thickness, and wherein the thickness is approximately less than 0.01 mm.

6. The semiconductor device of claim 1 , wherein the interlock structure comprises an elongated slab structure.

7. The semiconductor device of claim 1 , wherein the interlock structure comprises a narrow portion adjoining a widened portion, and wherein the widened portion is configured to engage the semiconductor die.

8. The semiconductor device of claim 7 , wherein the widened portion comprises a groove.

9. The semiconductor device of claim 1 , wherein the interlock structure has a height of approximately between 0.001 mm and 0.05 mm.

10. The semiconductor device of claim 1 forms a portion of a lighting system.

11. A device, comprising:

a die attach pad;

a die attach surface of the die attach pad;

an interlock structure formed on the die attach surface;

a semiconductor die configured to be mounted on the die attach surface;

a die attach glue configured to adjoin the semiconductor die and the die attach pad; and

an encapsulant covering the die attach pad, the die attach glue and the semiconductor die,

wherein the interlock structure is configured to engage the die attach glue so as to provide a mechanical interlock interlocking the die attach pad and the die attach glue.

12. The device of claim 11 , wherein the die attach pad further comprises a die support structure formed adjacent to the interlock structure on the die attach surface, and wherein the die support structure is configured to engage the semiconductor die.

13. The device of claim 12 , wherein the interlock structure is formed between the semiconductor die and the die attach surface, and wherein the interlock structure is distanced away from the semiconductor die.

14. The device of claim 11 , wherein the semiconductor die is mounted on the die attach surface adjacent to the interlock structure.

15. The device of claim 14 further comprises an additional interlock structure, and wherein the semiconductor die is interposed between the interlock structure and the additional interlock structure.

16. The device of claim 14 further comprises an additional semiconductor die, and wherein the interlock structure is interposed between the semiconductor die and the additional semiconductor die.

17. The device of claim 11 , wherein the interlock structure comprise a body portion configured to engage the semiconductor die, and a wing portion configured to engage the die attach glue so as to provide the mechanical interlock.

18. The device of claim 17 , wherein the wing portion comprises a bend.

19. The device of claim 11 , wherein the interlock structure is formed beneath the die attach surface and distanced away from the semiconductor die.

20. A light-emitting device, comprising

a die attach pad;

an emitter mounted on the die attach pad;

a plurality of leads electrically coupled to the emitter;

an adhesive material in direct contact with a portion of the die attach pad and the emitter so as to adjoin the emitter and the die attach pad; and

a substantially transparent encapsulant encapsulating the emitter, the adhesive material and at least a portion of the die attach pad,

wherein the die attach pad comprises an interlock structure providing a mechanical interlock with the adhesive material so as to mechanically adjoin the die attach pad and the adhesive material.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2014
From: NG, KEAT CHUAN; ONG, KIAM SOON; TAN, KHENG LENG
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 032207/0899 →
Continuity (1)
Related Publication 20150228611A1 · Aug 13, 2015