Linear and DC-accurate frontend DAC and input structure
View Patent ↗A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.
1. A current element, comprising:
a current source;
a plurality of switches arranged to form two circuit branches between the current source and a first and a second outputs, wherein:
the first circuit branch includes two switches defining parallel current paths between the current source and the first output terminal,
the second circuit branch includes two switches defining parallel current paths between the current source and the second output terminal, and
a control circuit, responsive to an input signal that selects one of the circuit branches, providing control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.
2. The current element of claim 1 , wherein the current source is a resistor.
3. The current element of claim 1 , wherein at least one current path changes state between each cycle of a driving clock.
4. The current element of claim 1 , wherein at least one current path changes state between each phase of a driving clock.
5. The current element of claim 1 , wherein the switches that are activated in one cycle are activated for a common duration.
6. The current element of claim 1 , wherein:
the two switches in the first circuit branch are activated consecutively during one cycle to provide a first state in which the current source is coupled to the first output terminal, and
the two switches in the second circuit branch are activated consecutively during one cycle to provide a second state in which the current source is coupled to the second output terminal.
7. The current element of claim 1 , further comprising an additional switch forming a third branch between the current source and a dump node.
8. The current element of claim 1 , wherein the switches are one of NMOS switch and PMOS switch.
9. A current element, comprising:
a first current source;
a second current source;
a plurality of circuit branches connected between the first current source and the second current source, wherein:
a first circuit branch defines two parallel current paths, each current path including one switch connected between the first current source and a first output terminal and another switch connected between the second current source and the first output terminal;
a second circuit branch defines two parallel current paths, each current path including one switch connected between the first current source and a second output terminal and another switch connected between the second current source and the second output terminal; and
a controller, responsive to an input signal that selects one of the first and second current sources to be connected to the first output terminal and selects the other of the first and second current sources to be connected to the second output terminal, the controller providing control signals to the switches in the circuit branch that is connected to the first output terminal to pass current through a first parallel current path in a first portion of a clock cycle and to pass current through a second parallel current path in a second portion of the clock cycle and providing control signals to the switches in the circuit branch that is connected to the second output terminal to pass current through a first parallel current path thereof in the first portion of a clock cycle and to pass current through a second parallel current path thereof in the second portion of the clock cycle.
10. The current element of claim 9 , wherein the first and second current sources are resistors.
11. The current element of claim 9 , wherein the switches that are activated consecutively in one clock cycle are activated for a common duration.
12. The current element of claim 9 , wherein at least one current path changes state between each cycle of a driving clock.
13. The current element of claim 9 , wherein at least one current path changes state between each phase of a driving clock.
14. The current element of claim 9 , wherein the switches are one of NMOS switch and PMOS switch.
15. The current element of claim 9 , wherein the first and second output terminals provide a differential output signal.
16. A digital-to-analog converter, comprising:
a plurality of current elements for converting digital data into an analog signal, each current element including:
a current source;
a plurality of switches arranged to form two circuit branches between the current source and a first and a second outputs, wherein:
the first circuit branch includes two switches defining parallel current paths between the current source and the first output terminal,
the second circuit branch includes two switches defining parallel current paths between the current source and the second output terminal, and
a control circuit, responsive to an input signal that selects one of the circuit branches, providing control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle;
an adder for adding analog signals output from each of the current elements.
17. The digital-to-analog converter of claim 16 , wherein the current source is a resistor.
18. The digital-to-analog converter of claim 16 , wherein at least one current path changes state between each cycle of a driving clock.
19. The digital-to-analog converter of claim 16 , wherein at least one current path changes state between each phase of a driving clock.
20. The digital-to-analog converter of claim 16 , wherein each current element further includes an additional switch forming a third branch between the current source and a dump node.
21. The digital-to-analog converter of claim 16 , wherein the switches in the unit elements are one of NMOS switch and PMOS switch.
22. A circuit comprising, comprising:
an integrator receiving a current signal from an input node representing a difference between an input signal and a feedback signal;
an analog-to-digital converter (ADC) circuit coupled to an output of the integrator;
a digital-to-analog converter (DAC) circuit coupled to the output of the ADC circuit and providing the feedback signal to the input node, comprising a plurality of current elements controlled by an output signal from the ADC and comprising:
a current source; and
a circuit branch(es) coupling the current source to output terminal(s) of the current element, each circuit branch comprising a plurality of parallel circuit paths extending between the current source and the respective output terminal;
a driver circuit to control switching within the circuit branch(es) in response to the ADC output signal wherein, during first phase of a clock cycle, a first parallel circuit path conducts current to an output terminal and, during a second phase of the clock cycle, a second parallel circuit path conducts current to the output terminal.
23. The circuit of claim 22 , wherein the current source is a resistor.
24. The circuit of claim 22 , wherein the driver control the switching within the circuit branch(es) such that at least one current path changes state between each cycle of a driving clock.
25. The circuit of claim 22 , wherein the driver control the switching within the circuit branch(es) such that at least one current path changes state between each phase of a driving clock.
26. The circuit of claim 22 , further comprising an input switch structure coupling an input resistor to the integrator.
27. The circuit of claim 22 , wherein the input switch structure includes a plurality of switches and the switches are controlled in synchronization with the switches in the unit elements.