Fine-grained bit-rate control
View Patent ↗A system implements rate control for encoding and decoding operations, for example, operations performed on slices of data such as image data. The system implements fine-grained bit rate control allowing for non-integer bit rates to be specified for the system. The non-integer values may allow the system to more accurately characterize a data rate of a communication link between a source and sink. The more accurate characterization may facilitate improved utilization of the communication link capacity.
1. A method implemented by an encoding device, the method comprising:
determining a fractional bit rate comprising a rate integer portion corresponding to an integer bit rate and a rate fractional portion corresponding to a non-integer bit rate;
accumulating the rate fractional portion of an input stream in a buffer;
determining when accumulating the rate fractional portion of the input stream results in an accumulated integer portion; and
reducing a buffer fullness associated with encoding the input stream by the rate integer portion and the accumulated integer portion.
2. The method of claim 1 , further comprising:
accumulating a second fractional portion; and
combining the rate fractional portion and second fractional portion to generate the accumulated integer portion.
3. The method of claim 1 , wherein determining the fractional bit rate comprises determining a number of bits for a unit.
4. The method of claim 3 , wherein the determining the number of bits for the unit comprises determining a number of pixels for the unit.
5. The method of claim 1 , further comprising increasing a bit budget by one or more adjustment bits to facilitate aligning an end of a bitstream chunk to a byte boundary.
6. The method of claim 5 , wherein reducing the buffer fullness by the rate integer portion comprises subtracting the rate integer portion from the accumulated integer portion.
7. The method of claim 1 , wherein:
the buffer fullness comprises a virtual buffer fullness; and
the method further comprises modeling content of a memory buffer.
8. The method of claim 7 , further comprising increasing the virtual buffer fullness by a third integer portion responsive to the encoding device adding data to the memory buffer.
9. The method of claim 1 , further comprising determining a quantization parameter based at least in part on the buffer fullness.
10. The method of claim 1 , wherein determining the fractional bit rate comprises determining an effective data rate for a communication link that transfers data out of a memory buffer.
11. The method of claim 10 , wherein determining the effective data rate comprises determining an average data rate of the communication link.
12. The method of claim 10 , further comprising adjusting the fractional bit rate responsive to a change in a condition of the communication link.
13. The method of claim 1 , wherein the buffer comprises a rate accumulator and the method further comprises setting a granularity of the fractional bit rate in inverse powers of two by selecting a number of significant fractional bits for the rate accumulator.
14. The method of claim 13 , wherein accumulating the rate fractional portion comprises setting one or more of the significant fractional bits of the rate accumulator.
15. An encoding system, comprising:
a memory buffer configured to store data;
fractional rate circuity coupled to the memory buffer, the fractional rate circuitry configured to:
determine a fractional bit rate comprising a rate integer portion and a rate fractional portion, wherein the fractional bit rate comprises a fractional number of bits per unit time corresponding to a constant rate channel;
accumulate the rate fractional portion;
determine when accumulating the rate fractional portion results in an accumulated integer portion; and
reduce a buffer fullness for the memory buffer by the rate integer portion and the accumulated integer portion.
16. The encoding system of claim 15 , where:
the system further comprises a communication interface configured to establish a communication link that transfers data out of the memory buffer; and
fractional rate circuity is further configured to determine the fractional bit rate by determining an effective data rate for the communication link.
17. A method implemented by an encoding device, the method comprising:
based on a data stream from a source, determining a fractional bit rate for the data stream, the fractional bit rate comprising a rate integer portion and a rate fractional portion that comprises a fractional value;
increasing virtual buffer fullness to represent data being added to a memory buffer; reducing the virtual buffer fullness by the rate integer portion and the rate fractional portion of the fractional bit rate to model removal of the data from the memory buffer;
accumulating the data stream at the rate fractional portion of the fractional bit rate;
determining when accumulating the data stream at the rate fractional portion results in an accumulated integer portion; and
responsive to the accumulated integer portion, reducing the virtual buffer fullness by the accumulated integer portion.
18. The method of claim 17 , further comprising:
determining an effective data rate for the data stream based on a communication link configured to transport the data stream; and
based on the effective data rate for the data stream, determining the fractional bit rate.
19. The method of claim 17 , further comprising setting a granularity of the fractional bit rate in inverse powers of two by selecting a number of significant fractional bits for a rate accumulator.