IP Library Granted Patent US 9,673,155
Granted Patent B2
US 9,673,155 · App. 14/181,332 · Granted Jun 6, 2017

Integrated tunable filter architecture

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,673,155
App. No.
14/181,332
Granted
Jun 6, 2017
Kind
B2
Abstract

An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.

Claims (23)

1. An integrated circuit configuration including:

(a) a frequency based circuit having a common signal path;

(b) at least one tunable filter coupled to the common signal path of the frequency based circuit, wherein each tunable filter is configured to be selectively activated to filter unwanted frequencies from the common signal path of the frequency based circuit; and

(c) a bypassable low-pass filter coupled to the common signal path for filtering out a broad range of high frequencies from the common signal path that may adversely affect the frequency based circuit;

wherein the frequency based circuit, each tunable filter, and the bypassable low-pass filter are co-designed to absorb and compensate for residual and other parasitic impedances present in the integrated circuit configuration so as to have a total insertion loss that is less than a total insertion loss that would exist if the at least one tunable filter or the bypassable low-pass filter were external to the integrated circuit configuration.

2. An integrated circuit configuration including:

(a) a frequency based circuit having a common signal path;

(b) at least one tunable filter means coupled to the common signal path of the frequency based circuit, for selectively filtering unwanted frequencies from the common signal path of the frequency based circuit; and

(c) a bypassable low-pass filter means coupled to the common signal path for filtering out a broad range of high frequencies from the common signal path that may adversely affect the frequency based circuit;

wherein the frequency based circuit, each tunable filter means, and the bypassable low-pass filter means are co-designed to absorb and compensate for residual and other parasitic impedances present in the integrated circuit configuration so as to have a total insertion loss that is less than a total insertion loss that would exist if the at least one tunable filter means or the bypassable low-pass filter means were external to the integrated circuit configuration.

3. An integrated circuit configuration including:

(a) a frequency based circuit having a common signal path;

(b) at least one digitally tunable filter coupled to the common signal path of the frequency based circuit, wherein each digitally tunable filter is configured to be selectively activated to filter unwanted frequencies from the common signal path of the frequency based circuit; and

(c) a bypassable low-pass filter coupled to the common signal path for filtering out a broad range of high frequencies from the common signal path that may adversely affect the frequency based circuit;

wherein the frequency based circuit and each digitally tunable filter are co-designed to absorb and compensate for residual and other parasitic impedances present in the integrated circuit configuration so as to have a total insertion loss that is less than a total insertion loss that would exist if the at least one digitally tunable filter was external to the integrated circuit configuration.

4. An integrated circuit including:

(a) at least one tunable filter configured to be coupled to a common signal path of a frequency based circuit, wherein each tunable filter is configured to be selectively activated to filter unwanted frequencies from the common signal path of the frequency based circuit; and

(b) a bypassable low-pass filter configured to be coupled to the common signal path for filtering out a broad range of high frequencies from the common signal path that may adversely affect the frequency based circuit;

wherein each tunable filter and the bypassable low-pass filter are designed to absorb and compensate for residual and other parasitic impedances present when coupled to the frequency based circuit so as to have a total insertion loss that is less than a total insertion loss that would exist if the at least one tunable filter or the bypassable low-pass filter were external to the integrated circuit.

5. An integrated circuit including:

(a) at least one digitally tunable filter configured to be coupled to a common signal path of a frequency based circuit wherein each digitally tunable filter is configured to be selectively activated to filter unwanted frequencies from the common signal path of the frequency based circuit; and

(b) a bypassable low-pass filter configured to be coupled to the common signal path for filtering out a broad range of high frequencies from the common signal path that may adversely affect the frequency based circuit;

wherein each digitally tunable filter and the bypassable low-pass filter are designed to absorb and compensate for residual and other parasitic impedances present when coupled to the frequency based circuit within an integrated circuit package so as to have a total insertion loss that is less than a total insertion loss that would exist if the at least one digitally tunable filter and the bypassable low-pass filter were external to the integrated circuit package.

Assignments (2)
CHANGE OF NAME Recorded Jan 24, 2018
From: PEREGRINE SEMICONDUCTOR CORPORATION
To: PSEMI CORPORATION
Reel/Frame 045749/0391 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2014
From: SMITH, WILLIAM R.; ADAMSKI, JAROSLAW; NOBBE, DAN WILLIAM; COMFOLTEY, EDWARD NICHOLAS; WANG, JINGBO
To: PEREGRINE SEMICONDUCTOR CORPORATION
Reel/Frame 032824/0496 →