Electrical connectivity for circuit applications
View Patent ↗According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
1. A method comprising:
receiving a leadframe component comprising: a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other;
receiving a semiconductor chip substrate including a first array of switch circuits disposed substantially side-by-side with respect to a second array of switch circuits, source nodes in switch circuits of the first array being disposed substantially side-by-side with respect to source nodes in switch circuits of the second array; and
electrically coupling each of the source nodes in switch circuits of the first array and each of the source nodes in switch circuits of the second array to the second conductive strip.
2. The method as in claim 1 further comprising:
electrically coupling drain nodes in switch circuits of the first array to the first conductive strip; and
electrically coupling drain nodes in switch circuits of the second array to the third conductive strip.
3. The method as in claim 2 further comprising:
electrically coupling the first conductive strip, the second conductive strip, and the third conductive strip to a host circuit board to electrically couple the first conductive strip and the third conductive strip to each other, the second conductive strip being electrically isolated from the first conductive strip and the third conductive strip.
4. The method as in claim 3 , wherein a row of the source nodes in the first array and a row of the source nodes in the second array are disposed on the semiconductor chip substrate between a row of drain nodes of the first array and a row of drain nodes of the second array.
5. The method as in claim 4 further comprising:
aligning the source nodes of the first array and the source nodes of the second array over the second conductive strip.
6. The method as in claim 1 further comprising:
aligning the source nodes of the first array and the source nodes of the second array over a surface region of the second conductive strip.
7. The method as in claim 1 , wherein the semiconductor chip substrate includes a first face and a second face, each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array disposed on the first face;
wherein the leadframe includes a first face and a second face, the first face of the leadframe including a first contact region, a second contact region, and a third contact region, the first contact region being a surface of the first conductive strip, the second contact region being a surface of the second conductive strip, the third contact region being a surface of the third conductive strip; and
wherein electrically coupling each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to the second conductive strip includes: disposing the first face of the semiconductor chip substrate to face the first face of the lead frame.
8. The method as in claim 7 , wherein electrically coupling further comprises:
providing conductive bridge elements electrically connecting each of the source nodes of the first array to the second contact region; and
providing conductive bridge elements electrically connecting each of the source nodes of the second array to the second contact region.
9. The method as in claim 8 further comprising:
providing conductive bridge elements electrically connecting each of multiple drain nodes of the switch circuits in the first array to the first contact region; and
providing conductive bridge elements electrically connecting each of multiple drain nodes of the switch circuits in the second array to the third contact region.
10. The method as in claim 9 , wherein the second face of the leadframe includes a first exposed surface, a second exposed surface, and a third exposed surface; and
wherein the first exposed surface is a first pad of the first conductive strip, the second exposed surface is a second pad of the second conductive strip, and the third exposed surface is a third pad of the third conductive strip, the method further comprising:
electrically contacting the first pad and the third pad to a first trace on the host substrate; and
electrically contacting the second pad to a second trace on the host substrate, the second trace electrically isolated from the first trace.
11. A method comprising:
disposing a first array of switch circuits on a semiconductor chip substrate, each switch circuit in the first array including a source node and a drain node; and
disposing a second array of switch circuits on the semiconductor chip substrate, each switch circuit in the second array including a source node and a drain node, a sequence of the source nodes in switch circuits of the first array disposed on a face of the semiconductor chip substrate side-by-side with respect to the sequence of source nodes in switch circuits of the second array.
12. The method as in claim 11 further comprising:
producing each switch circuit in the first array to include a respective set of transistors electrically connected in parallel with each other; and
producing each switch circuit in the second array of switch circuits to include a respective set of transistors electrically connected in parallel with each other.
13. The method as in claim 12 further comprising:
fabricating the first array of switch circuits to be side-by-side with respect to the second array of switch circuits on the semiconductor chip substrate; and
disposing the sequence of source nodes of the first array and the sequence of source nodes of the second array on the face of the semiconductor chip substrate to be between a row of drain nodes of the first array and a row of drain nodes of the second array, the row of drain nodes of the first array disposed side-by-side with respect to the row of drain nodes of the second array.
14. The method as in claim 13 further comprising:
producing each switch circuit in the first array to be electrically isolated from each other prior to coupling of the semiconductor chip substrate to a leadframe package device; and
producing each switch circuit in the second array to be electrically isolated from each other prior to coupling of the semiconductor chip substrate to the leadframe package device.
15. The method as in claim 11 further comprising:
disposing the sequence of source nodes of the first array and the sequence of source nodes of the second array of the semiconductor chip substrate between a sequence of drain nodes of the first array and a sequence of drain nodes of the second array, the sequence of drain nodes of the first array and the sequence of drain nodes of the second array disposed on the face of the semiconductor chip substrate; and
producing each respective switch circuit in the first array of switch circuits to include a respective set of transistors connected in parallel with each other; and
producing each switch circuit in the second array of switch circuits to include a respective set of transistors connected in parallel with each other.
16. The method as in claim 11 further comprising:
producing each switch circuit in the first array to be electrically isolated from each other prior to coupling of the semiconductor chip substrate to a leadframe package device; and
producing each switch circuit in the second array to be electrically isolated from each other prior to coupling of the semiconductor chip substrate to a leadframe package device.
17. The method as in claim 13 further comprising:
disposing a sequence of the switch circuits in the first array to be substantially linear on a face of the semiconductor chip substrate;
disposing a sequence of the switch circuits in the second array to be substantially linear on the face of the semiconductor chip substrate;
disposing the first array and the second array to be side-by-side with respect to each other on the face; and
disposing the sequence of drain nodes of the first array and the sequence of drain nodes of the second array to be substantially parallel to each other on the face of the semiconductor chip substrate.
18. The method as in claim 2 , wherein the source nodes in switch circuits of the first array is a first sequence of source nodes;
wherein the source nodes in switch circuits of the second array is a second sequence of source nodes;
wherein the source nodes in switch circuits of the first array and the source nodes in switch circuits of the second array lie within a contiguous region on the face of the semiconductor chip substrate, the source nodes in switch circuits of the first array and the source nodes in switch circuits of the second array aligning with a surface of the second conductive strip.
19. The method as in claim 11 further comprising:
fabricating the source nodes in switch circuits of the first array and the source nodes in switch circuits of the second array to lie within a contiguous region on the face of the semiconductor chip substrate, the contiguous region fabricated to correspond to a surface of a conductive strip to which the source nodes in switch circuits of the first array and the source nodes in switch circuits of the second array are configured to attach.
20. The method as in claim 11 further comprising:
fabricating the sequence of source nodes in switch circuits of the first array to be electrically isolated from the sequence of source nodes of switch circuits of the second array prior to coupling of the semiconductor chip substrate to a leadframe package device.