Nonvolatile semiconductor storage device and control method thereof

1. A nonvolatile semiconductor storage device, comprising:

a nonvolatile memory cell array, having a plurality of memory cells connected to global bit lines;

a page buffer circuit, having a first latch circuit temporarily storing data read from and written to the nonvolatile memory cell array by a predetermined page unit;

a second latch circuit, temporarily storing data input from and output to an external circuit; and

a control circuit, controlling data reading and writing of the nonvolatile memory cell array,

wherein the nonvolatile memory cell array is divided into a first cell array and a second cell array, the page buffer circuit is arranged between the first cell array and the second cell array, and the second latch circuit is arranged by the outside edge section of the first cell array;

the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array;

the control circuit controls data writing to the first cell array or the second cell array by transmitting the writing data to the page buffer circuit from the second latch circuit via the global bit line of the first cell array, after the writing data from the external circuit is latched in the second latch circuit, for data writing; and

the control circuit controls outputting the data read from the first cell array or the second cell array to the external circuit by transmitting data to the second latch circuit from the page buffer circuit via the global bit line of the first cell array, for data reading.

2. The nonvolatile semiconductor storage device of claim 1 , wherein the control circuit controls performing a time division operation of at least one of data writing, data reading and data erasing for the first cell array and the second cell array.

3. The nonvolatile semiconductor storage device of claim 2 , wherein the control circuit controls each timing of data programming and verifying with time shifts between the first cell array and the second cell array by a predetermined delay time.

4. The nonvolatile semiconductor storage device of claim 2 , wherein the control circuit controls the data verification for the second cell array at the time of data writing for the first cell array, or controls the data verification for the first cell array at the time of data writing for the second cell array.

5. The nonvolatile semiconductor storage device of claim 2 , wherein the control circuit controls data erasing for the first cell array and the second cell array simultaneously, and performing data verification for the first cell array and the second cell by the time division operation.

6. The nonvolatile semiconductor storage device of claim 1 , wherein the page buffer circuit further comprises a third latch circuit storing shunted data of another cell array when one of the first cell array and the second cell array performs data writing or data reading.

7. The nonvolatile semiconductor storage device of claim 6 , wherein the third latch circuit further comprises a plurality of latches for memory cells in an MLC of storing data of a plurality of bits for each of the memory cells.

8. The nonvolatile semiconductor storage device of claim 6 , wherein the third latch circuit further comprises a global bit line of the first cell array or the second cell array, and a switch unit, and the third latch circuit is constructed by a dynamic latch circuit composed of a stray capacitance of the global bit line of the first cell array or the second cell array and the switch unit.

9. The nonvolatile semiconductor storage device of claim 6 , wherein the control circuit directly transmits data from the third latch circuit to the second latch circuit via the global bit line of the first cell array at the time of data reading.

10. A nonvolatile semiconductor storage device, comprising:

a nonvolatile memory cell array, having a plurality of memory cells connected to global bit lines;

a page buffer circuit, having a first latch circuit temporarily storing data read from and written to the nonvolatile memory cell array by a predetermined page unit;

a second latch circuit, temporarily storing data input from and output to an external circuit; and

a control circuit, controlling data reading and writing of the nonvolatile memory cell array,

wherein the nonvolatile memory cell array is divided to a first cell array and a second cell array, the page buffer circuit is arranged between the first cell array and the second cell array, and the second latch circuit is arranged by the outside edge section of the first cell array;

the nonvolatile semiconductor storage device comprises a data bit line connecting the page buffer circuit to the second latch circuit;

the control circuit controls data writing to the first cell array or the second cell array by transmitting the writing data to the page buffer circuit from the second latch circuit via the data bit line, after the writing data from the external circuit is latched in the second latch circuit, for data writing; and

the control circuit controls outputting the data read from the first cell array or the second cell array to the external circuit by transmitting data from the page buffer circuit to the second latch circuit via the data bit line, for data reading.

11. The nonvolatile semiconductor storage device of claim 10 , wherein the control circuit controls performing a time division operation of at least one of data writing, data reading and data erasing for the first cell array and the second cell array.

12. The nonvolatile semiconductor storage device of claim 11 , wherein the control circuit controls each timing of data programming and verifying with time shifts between the first cell array and the second cell array by a predetermined delay time.

13. The nonvolatile semiconductor storage device of claim 11 , wherein the control circuit controls the data verification for the second cell array at the time of data writing for the first cell array, or controls the data verification for the first cell array at the time of data writing for the second cell array.

14. The nonvolatile semiconductor storage device of claim 11 , wherein the control circuit controls data erasing for the first cell array and the second cell simultaneously, and performing data verification for the first cell array and the second cell by the time division operation.

15. The nonvolatile semiconductor storage device of claim 10 , wherein page buffer circuit further comprises a third latch circuit storing shunted data of another cell array when one of the first cell array and the second cell performs data writing or data reading.

16. The nonvolatile semiconductor storage device of claim 15 , wherein the third latch circuit further comprises a plurality of latches for memory cells in an MLC of storing data of a plurality of bits for each of the memory cells.

17. The nonvolatile semiconductor storage device of claim 15 , wherein the page buffer circuit further comprises another data bit line other than the data bit line connecting the page buffer circuit to the second latch circuit, and a switch unit controlling the connection of the page buffer circuit.

18. The nonvolatile semiconductor storage device of claim 17 , wherein the third latch circuit comprises the data bit line or the other data bit line and the switch unit; and the third latch circuit is constructed by a dynamic latch circuit composed of a stray capacitance of the stray capacitance of the data bit line or the other data bit line and the switch unit.

19. The nonvolatile semiconductor storage device of claim 15 , wherein the third latch circuit further comprises a global bit line of the first cell array or the second cell array, and a switch unit; and the third latch circuit is constructed by a dynamic latch circuit composed of a stray capacitance of the global bit line of the first cell array or the second cell array and the switch unit.

20. The nonvolatile semiconductor storage device of claim 15 , wherein the control circuit directly transmits data from the third latch circuit to the second latch circuit via the data bit line at the time of data reading.

21. A control method for a nonvolatile semiconductor storage device comprising a nonvolatile memory cell array having a plurality of memory cells connected to global bit lines, a page buffer circuit having a first latch circuit temporarily storing data read from and written to the nonvolatile memory cell array by a predetermined page unit, a second latch circuit temporarily storing data input from and output to an external circuit; and a control circuit controlling data reading and writing of the nonvolatile memory cell array, the nonvolatile memory cell array is divided into a first cell array and a second cell array, the page buffer circuit is arranged between the first cell array and the second cell array, the second latch circuit is arranged by the outside edge section of the first cell array, the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array, wherein the control method comprises:

using the control circuit to control data writing to the first cell array or the second cell array by transmitting the writing data to the page buffer circuit from the second latch circuit via the global bit line of the first cell array, after the writing data from the external circuit is latched in the second latch circuit, for data writing; and

using the control circuit to control outputting the data read from the first cell array or the second cell array to the external circuit by transmitting data to the second latch circuit from the page buffer circuit via the global bit line of the first cell array, for data reading.

22. A control method for a nonvolatile semiconductor storage device comprising a nonvolatile memory cell array having a plurality of memory cells connected to global bit lines, a page buffer circuit having a first latch circuit temporarily storing data read from and written to the nonvolatile memory cell array by a predetermined page unit, a second latch circuit temporarily storing data input from and output to an external circuit, and a control circuit controlling data reading and writing of the nonvolatile memory cell array, the nonvolatile memory cell array is divided into a first cell array and a second cell array, the page buffer circuit is arranged between the first cell array and the second cell array, the second latch circuit is arranged by the outside edge section of the first cell array, the nonvolatile semiconductor storage device comprises a data bit line connecting the page buffer circuit to the second latch circuit, wherein the control method comprises:

using the control circuit to control data writing to the first cell array or the second cell array by transmitting the writing data to the page buffer circuit from the second latch circuit via the data bit line, after the writing data from the external circuit is latched in the second latch circuit, for data writing; and

using the control circuit to control outputting the data read from the first cell array or the second cell array to the external circuit by transmitting data to the second latch circuit from the page buffer circuit via the data bit line, for data reading.