Receiver and transmission and reception system
A receiver is composed of a receiver-side amplifier which receives a clock signal, a receiver-side amplifier which receives a data signal, a variable delay circuit which generates a delay-adjusted clock signal and a delay-adjusted data signal by delaying the clock signal and the data signal, a latch circuit section which latches the delay-adjusted data signal in synchronous with the delay-adjusted clock signal, and a skew detecting circuit which generates skew detection data that by latching a specific data sequence transmitted as the data signal in synchronous with a first clock signal to N th clock signal (N is an integer equal to or more than 2) with different delay times from the clock signal. The delay time in the variable delay circuit is controlled according to the skew detection data.
1. A receiver comprising:
a first receiving section configured to receive an external clock signal and output a clock signal;
a second receiving section configured to receive an external data signal and output a data signal;
a variable delay circuit configured to generate a delay-adjusted clock signal and a delay-adjusted data signal by delaying at least one of the clock signal and the data signal;
a latch circuit section configured to latch the delay-adjusted data signal in synchronization with the delay-adjusted clock signal to output an output data signal; and
a skew detecting circuit configured to latch a specific data sequence transmitted as the data signal or the delayed data signal obtained by delaying the data signal, in synchronization with first to N th clock signals (N is an integer equal to or more than 2) with different delay times to the clock signal to generate skew detection data, and control the variable delay circuit to adjust a delay time of the at least one signal based on the skew detection data.
2. The receiver according to claim 1 , wherein the skew detecting circuit generates a control signal to control the variable delay circuit to adjust the delay time of the at least one of the clock signal and the data signal based on the skew detection data,
wherein the variable delay circuit generates the first to N th clock signals and selects either of the first to N th clock signals based on the control signal, to output as the delay-adjusted clock signal, and
wherein the the first to N th clock signals are supplied from the variable delay circuit to the skew detecting circuit.
3. The receiver according to claim 2 , wherein the variable delay circuit generates the delayed data signal by delaying the data signal for a predetermined time period and the delay-adjusted data signal from the delayed data signal,
wherein the delayed data signal is supplied from the variable delay circuit to the skew detecting circuit, and
wherein the skew detecting circuit generates the skew detection data by latching the specific data sequence transmitted with the delayed data signal in synchronization with the first to N th clock signals.
4. The receiver according to claim 1 , wherein the skew detecting circuit generates and outputs the control signal to control the delay time of the at least one of the clock signal and the data signal to the variable delay circuit based on the skew detection data,
wherein the variable delay circuit comprises:
a data variable delay section configured to generate the delay-adjusted data signal by delaying the data signal; and
a clock variable delay section configured to generate the delay-adjusted clock signal by delaying the clock signal,
wherein the data variable delay section comprises:
a first delay circuit configured to output a first delay signal by delaying the data signal by a first delay time;
a second delay circuit configured to output a second delay signal by delaying the first delay signal by a second delay time; and
a first selecting circuit configured to select either one of the first delay signal and the second delay signal as the delay-adjusted data signal based on the control signal,
wherein the clock variable delay section comprises:
a third delay circuit configured to output a third delay signal by delaying the clock signal by the first delay time;
a fourth delay circuit configured to output a fourth delay signal by delaying the clock signal by the second delay time; and
a second selecting circuit configured to select either of the third delay signal and the fourth delay signal as the delay-adjusted clock signal based on the control signal, and
wherein the second delay time substantively coincides with a half of one period of the clock signal.
5. The receiver according to claim 4 , further comprising:
a first sequential delay section configured to generate a plurality of first sequential delay signals with different delay times to the clock signal from the clock signal;
a delay control data acquiring section configured to acquire a delay control data by latching the clock signal in synchronization with the plurality of first sequential delay signals, or the plurality of first sequential delay signals in synchronization with the clock signal;
a timing detecting circuit; and
a first delay selecting circuit,
wherein the second delay circuit comprises a second sequential delay section configured to generate a plurality of second sequential delay signals with different delay times to the first delay signal from the first delay signal,
wherein the timing detecting circuit determines either of the plurality of second sequential delay signals as the second delay signal in response to the delay control data, and
wherein the first delay selecting circuit outputs either of the plurality of second sequential delay signals as the second delay signal based on the determination by the timing detecting circuit.
6. The receiver according to claim 5 , wherein the fourth the delay circuit comprises:
a third sequential delay section configured to generate a plurality of third sequential delay signals with different delay times to the third delay signal from the third delay signal; and
a second delay selecting circuit,
wherein the timing detecting circuit determines either of the plurality of third sequential delay signals as the third delay signal in response to the delay control data, and
wherein the second delay selecting circuit outputs either of the plurality of third sequential delay signals as the third delay signal based on the determination by the timing detecting circuit.
7. The receiver according to claim 1 , wherein the transmission of the external clock signal and the external data signal to the receiver is carried out based on the MIPI (Mobile Industry Processor Interface) D-PHY standard and the specific data sequence is a data sequence which is contained in the HY-SYNC code.
8. The receiver according to claim 1 , further comprising:
a first signal line connected to the skew detecting circuit to supply the data signal or the delayed data signal;
a second signal line connected to the skew detecting circuit to supply the clock signal;
a first switch provided in the first signal line; and
a second switch provided in the second signal line,
wherein the skew detecting circuit is configured to generate and output the control signal to control the delay time of the at least one signal, to the variable delay circuit based on the skew detection data,
wherein the first switch and the second switch supplies the data signal or the delayed data signal to the skew detecting circuit and the clock signal to the skew detecting circuit in a specific period which contains a period for which the specific data sequence is transmitted,
wherein the first switch and the second switch block off supply of the data signal or the delayed data signal to the skew detecting circuit and supply of the clock signal to the skew detecting circuit in a period except the specific period, and
wherein the skew detecting circuit holds the value of the control signal in the period except the specific period.
9. The receiver according to claim 1 , further comprising:
a first signal line connected to the skew detecting circuit to supply the data signal or the delayed data signal;
a second signal line connected to the skew detecting circuit to supply first to N th clock signals;
a first switch provided in the first signal line; and
a second switch provided in the second signal line,
wherein the skew detecting circuit is configured to generate and output the control signal to control the delay time of the at least one signal to the variable delay circuit based on the skew detection data,
wherein the first switch and the second switch supply the data signal or the delayed data signal to the skew detecting circuit and the first to N th clock signals to the skew detecting circuit in a specific period which contains a period for which the specific data sequence is transmitted,
wherein the first switch and the second switch block off supply of the data signal or the delayed data signal to the skew detecting circuit and supply of the clock signal to the skew detecting circuit in a period except the specific period, and
wherein the skew detecting circuit holds a value of the control signal in the period except the specific period.
10. The receiver according to claim 1 , further comprising:
a third receiving section configure to receive a second external data signal and output a second data signal;
a second variable delay circuit configured to generate a second delay-adjusted data signal and a second delay-adjusted clock signal by delaying at least one of the clock signal and the second data signal;
a second latch circuit section configured to latch the second delay-adjusted data signal in synchronization with the second delay-adjusted clock signal to generate a second output data signal; and
a second skew detecting circuit configured to generate a second skew detection data by latching the specific data sequence transmitted by the second data signal or the second delayed data signal obtained by delaying the second data signal, in synchronization with first to N th clock signals (N is an integer equal to or more than 2) with different delay times to the clock signal, and control the delay time of the at least one signal in the second variable delay circuit based on the second skew detection data.
11. A receiver comprising:
a first receiving section configured to receive an external clock signal and output a clock signal;
a second receiving section configured to receive an external data signal and output a data signal;
a variable delay circuit configured to generate a delay-adjusted clock signal and a delay-adjusted data signal by delaying at least one of the clock signal and the data signal;
a latch circuit section configured to latch the delay-adjusted data signal in synchronization with the delay-adjusted clock signal to generate an output data signal; and
a skew detecting circuit configured to generate skew detection data by latching a specific data sequence transmitted with first to N th data signals (N is an integer equal to or more than 2) with different delay times to the data signal in synchronization with the clock signal or a delayed clock signal obtained by delaying the clock signal, and control a delay time of the at least one of the clock signal and the data signal based on the skew detection data.
12. The receiver according to claim 11 , wherein the skew detecting circuit generates a control signal to control the delay time of the at least one of the clock signal and the data signal by the variable delay circuit based on the skew detection data,
wherein the variable delay circuit generates the first to N th data signals and selects and outputs either of the first to N th data signals as the delay-adjusted data signal based on the control signal, and
wherein the first to N th data signals are supplied from the variable delay circuit to the skew detecting circuit.
13. The receiver according to claim 12 , wherein the variable delay circuit generates the delayed clock signal by delaying the clock signal by a predetermined time, and generates the delay-adjusted clock signal from the delayed clock signal,
wherein the delayed clock signal is supplied from the variable delay circuit to the skew detecting circuit, and
wherein the skew detecting circuit generates the skew detection data by latching the specific data sequence transmitted with the first to N th data signals in synchronization with the delayed clock signal.
14. A transmission and reception system comprising:
a transmitter; and
a receiver configured to receive an external clock signal and an external data signal from the transmitter, and
wherein the receiver comprises:
a first receiving section configured to receive the external clock signal and output a clock signal;
a second receiving section configured to receive the external data signal and output a data signal;
a variable delay circuit configured to generate a delay-adjusted clock signal and a delay-adjusted data signal by delaying at least one of the clock signal and the data signal;
a latch circuit section configured to latch the delay-adjusted data signal in synchronization with the delay-adjusted clock signal to output an output data signal; and
a skew detecting circuit configured to latch a specific data sequence transmitted with the data signal or the delayed data signal obtained by delaying the data signal in synchronization with first to N th clock signals (N is an integer equal to or more than 2) with different delay times to the clock signal to generate skew detection data, and control the variable delay circuit to adjust a delay time of the at least one signal based on the skew detection data.
15. The transmission and reception system according to claim 14 , wherein the transmission of the external clock signal and the external data signal from the transmitter to the receiver is carried out based on the MIPI (Mobile Industry Processor Interface) D-PHY standard, and the specific data sequence is a data sequence which is contained in the HY-SYNC code.
16. A transmission and reception system comprising:
a transmitter; and
a receiver configured to receive an external clock signal and an external data signal from the transmitter, and
wherein the receiver comprises:
a first receiving section configured to receive an external clock signal and output a clock signal;
a second receiving section configured to receive an external data signal and output a data signal;
a variable delay circuit configured to generate a delay-adjusted clock signal and a delay-adjusted data signal by delaying at least one of the clock signal and the data signal;
a latch circuit section configured to latch the delay-adjusted data signal in synchronization with the delay-adjusted clock signal to generate an output data signal; and
a skew detecting circuit configured to generate skew detection data by latching a specific data sequence transmitted with first to N th data signals (N is an integer equal to or more than 2) with different delay times to the data signal generated from the data signal, in synchronization with the clock signal or a delayed clock signal obtained by delaying the clock signal, and control a delay time of the at least one signal based on the skew detection data.
17. The transmission and reception system according to claim 16 , wherein the transmission of the external clock signal and the external data signal from the transmitter to the receiver is carried out based on the MIPI (Mobile Industry Processor Interface) D-PHY standard, and the specific data sequence is a data sequence which is contained in the HY-SYNC code.