INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION

1 . A system comprising:

an interleaved bit-stream generator adapted to receive a first digital input signal and output a switching signal, the interleaved-bit-stream generator comprising:

a fractional-delay array adapted to receive the first digital input signal and output a plurality of fractionally delayed digital output signals;

a bit-stream generation array adapted to receive the plurality of fractionally delayed digital output signals and output a plurality of corresponding bit-streams; and

a serializer block adapted to receive the plurality of corresponding bit-streams and interleave the bit-streams to generate the switching signal, wherein the frequency of the switching signal is higher than the frequency of the first digital input signal.

2 . The system of claim 1 , wherein the frequency of the switching signal is higher than the frequency of all of the plurality of corresponding bit-streams.

3 . The system of claim 1 , wherein:

the fractional-delay array comprises M fractional-delay filters, where M is an integer greater than 1;

the bit-stream generator array comprises M bit-stream generators;

each fractional-delay filter receives the first digital input signal, introduces a corresponding fractional delay Φ i , and provides a corresponding fractionally delayed digital output signal u i to a corresponding bit-stream generator;

i corresponds to the integers from 1 to M;

each bit-stream generator receives the corresponding fractionally delayed output signal u i and generates a corresponding bit-stream x i .

4 . The system of claim 3 , wherein:

the first digital input signal has a sampling frequency of Fs;

the first digital input signal has a sampling period Ts, wherein Ts=1/Fs; and

fractional delay Φ i of the ith fractional-delay filter is (i−1)/M of the sampling period.

5 . The system of claim 4 , wherein the output switching signal has a sampling frequency that is M*Fs.

6 . The system of claim 3 , wherein the respective fractional delays of the fractional-delay filters are set such that the switching signal is a band-pass signal.

7 . The system of claim 3 , wherein M is 8.

8 . The system of claim 3 , wherein each of the M fractional-delay filters is a tunable interpolation filter comprising a Farrow structure.

9 . The system of claim 3 , wherein:

M is an even integer;

the serializer block comprises a funneling cascade of 2-to-1 serializers;

the first stage of funneling cascade comprises M/2 2-to-1 serializers;

every subsequent stage of the funneling cascade comprises half the number of serializers of the previous stage; and

the final stage of the funneling cascade comprises one 2-to-1 serializer that outputs the switching signal.

10 . The system of claim 9 , wherein:

M is 8;

the serializer block comprises a funneling cascade of 7 2-to-1 serializers in three stages;

the first stage of the funneling cascade comprise 4 2-to-1 serializers;

the second stage of the funneling cascade comprise 2 2-to-1 serializers; and

the third of the funneling cascade comprise 1 2-to-1 serializer.

11 . The system of claim 3 , wherein:

A and B are integers between 1 and M, inclusive;

B=A+1; and

bit-stream signals x A and x B are interleaved to generate interleaved bit-stream signal x AB .

12 . The system of claim 11 , wherein the fractional delays Φ A and Φ B are selected so that the high-pass components in x AB substantially cancel out to make x AB a low-pass bit stream.

13 . The system of claim 11 , wherein the fractional delays Φ A and Φ B are selected so that the low-pass components in x AB substantially cancel out to make x AB a high-pass bit stream.

14 . The system of claim 11 , wherein:

the first digital input signal has a sampling frequency of Fs;

the first digital input signal has a frequency of f;

Φ A is 0; and

Φ B is f*π/Fs.

15 . The system of claim 11 , wherein:

the first digital input signal has a sampling frequency of Fs;

the first digital input signal has a frequency of f;

Φ A is 0; and

Φ B is f*π/Fs+π.

16 . The system of claim 11 , wherein:

the first digital input signal has a sampling frequency of Fs;

the first digital input signal has a frequency of f;

Φ A is 0; and

  1 B is f*π/Fs+π/2.

17 . The system of claim 11 , wherein:

the first digital input signal has a sampling frequency of Fs;

the first digital input signal has a frequency of f;

Φ A is 0; and

Φ B is f*π/Fs−π/2.

18 . The system of claim 1 , wherein:

the switching signal is a radio-frequency switching signal; and

the system further comprises:

a digital signal source adapted to generate the first digital input signal;

a switching power amplifier adapted to receive the switching signal and output a corresponding amplified radio-frequency signal;

a bandpass filter adapted to receive the amplified radio-frequency signal and output a corresponding analog radio-frequency output signal; and

an antenna adapted to receive the analog radio-frequency output signal and transmit a corresponding wireless radio-frequency signal.

19 . A method comprising:

receiving, by an interleaved bit-stream generator, a first digital input signal, wherein the interleaved bit-stream generator comprises:

a fractional-delay array;

a bit-stream generation array; and

a serializer block;

receiving, by the fractional-delay array, the first digital input signal;

outputting, by the fractional-delay array, a plurality of fractionally delayed digital output signals;

receiving, by the bit-stream generation array, the plurality of fractionally delayed digital output signals;

outputting, by the bit-stream generation array, a plurality of corresponding bit-streams;

receiving, by the serializer block, the plurality of corresponding bit-streams;

interleaving, by the serializer block, the plurality of bit-streams to generate a corresponding switching signal, wherein the frequency of the switching signal is higher than the frequency of the first digital input signal; and

outputting, by the interleaved bit-stream generator, the switching signal.