Vertical-type semiconductor apparatus and fabrication method thereof
View Patent ↗A semiconductor apparatus includes a semiconductor substrate including first and second regions, an inactive region formed in the semiconductor substrate of the second region and from a surface thereof, one or more first pillars vertically extending from the semiconductor substrate of the first region, one or more second pillars vertically extending from the inactive region, a gate conductive layer formed on the semiconductor substrate and surrounding the first and second pillars, and a gate contact formed on at least one of the second pillars to be coupled to the gate conductive layer, wherein the at least one of the second pillars has a height lower than the gate conductive layer.
1. A vertical-type semiconductor apparatus, comprising:
a semiconductor substrate including first region and second region;
an inactive region formed in the semiconductor substrate of the second region and formed from a surface thereof;
one or more first pillars vertically extending from the semiconductor substrate of the first region;
one or more second pillars vertically extending from the inactive region;
a gate conductive layer formed on the semiconductor substrate and surrounding the first and second pillars; and
a gate contact formed on at least one of the second pillars to be coupled to the gate conductive layer,
wherein the at least one of the second pillars has a height lower than the gate conductive layer.
2. The vertical-type semiconductor apparatus of claim 1 , further comprising:
a source contact electrically coupled to the semiconductor substrate and vertically extending from the surface of the semiconductor substrate, in a third region of the semiconductor substrate.
3. The vertical-type semiconductor apparatus of claim 2 , wherein the second region is defined to be adjacent to the first region in a horizontal direction, and the third region is defined to be adjacent to the second region in the horizontal direction.
4. The vertical-type semiconductor apparatus of claim 1 , further comprising:
one or more data storage units formed on the first pillars.
5. The vertical-type semiconductor apparatus of claim 4 , wherein the data storage unit includes a variable resistive layer.
6. The vertical-type semiconductor apparatus of claim 1 , further comprising:
an insulating layer formed between the semiconductor substrate and the gate conductive layer to surround lower ends of the first and second pillars.
7. A vertical-type semiconductor apparatus, comprising:
a semiconductor substrate including first and second regions;
one or more channel pillars vertically extending from the semiconductor substrate of the first region;
one or more insulating pillars vertically extending from the semiconductor substrate of the second region;
an inactive region formed to surround lower ends of the channel and insulating pillars;
a gate conductive layer formed on the inactive region and surrounding the channel and insulating pillars; and
a gate contact formed on at least one of the insulating pillars to be coupled to the gate conductive layer,
wherein the at least one of the insulating pillars has a height lower than the gate conductive layer and higher than the surface of the semiconductor substrate.
8. The vertical-type semiconductor apparatus of claim 7 , further comprising:
a source contact electrically coupled to the semiconductor substrate and vertically extending from the surface of the semiconductor substrate, in a third region of the semiconductor substrate.
9. The vertical-type semiconductor apparatus of claim 8 , wherein the second region is defined to be adjacent to the first region in a horizontal direction, and the third region is defined to be adjacent to the second region in the horizontal direction.
10. A method of fabricating a vertical-type semiconductor apparatus, the method comprising:
forming an inactive region having a first depth in a semiconductor substrate and formed from a surface thereof;
forming hard mask patterns on the semiconductor substrate including the inactive region and forming a plurality of pillars by patterning the semiconductor substrate and the inactive region to a second depth;
forming a gate conductive layer on an outer circumference of each of the plurality of pillars;
forming a first insulating layer on the semiconductor substrate including the gate conductive layer and planarizing the first insulating layer;
forming a gate contact hole by removing at least one of pillars formed on the inactive region to have a height lower than the gate conductive layer; and
forming a gate contact by burying a conductive material in the gate contact hole.
11. The method of claim 10 , wherein the vertical-type semiconductor substrate includes a first region adjacent to one side of the inactive region and a second region adjacent to the other side of the inactive region.
12. The method of claim 11 , further comprising:
removing a structure formed on the semiconductor substrate of the second region to expose the semiconductor substrate; and
forming a source contact coupled with the exposed semiconductor substrate and extending vertically from the surface of the semiconductor substrate.
13. The method of claim 11 , further comprising:
removing the hard mask patterns formed in the first region; and
forming a data storage unit in a space from which each hard mask pattern is removed.
14. The method of claim 10 , wherein the first depth is lower than the second depth from the surface of the semiconductor substrate.
15. The method of claim 10 , further comprising:
forming a second insulating layer on an outer circumference of a lower end of the each of the plurality of pillars,
wherein the gate conductive layer is formed on the insulating layer.
16. A method of fabricating a vertical-type semiconductor apparatus, the method comprising:
forming hard mask patterns on a semiconductor substrate in which a first region and a second region are defined, and forming a plurality of pillars by patterning the semiconductor substrate;
forming an inactive region of a first height to surround a lower end of each of the plurality of pillars;
forming a gate conductive layer of a second height on the inactive region to surround the pillar;
forming an insulating layer on the semiconductor substrate including the gate conductive layer and planarizing the insulating layer;
forming a gate contact hole by etching at least one of pillars formed in the second region to have a height lower than the gate conductive layer; and
forming a gate contact by burying a conductive material in the gate contact hole.
17. The method of claim 16 , wherein the first region is adjacent to one side of the second region, and the semiconductor substrate includes a third region adjacent to the other side of the second region.
18. The method of claim 17 , further comprising:
removing a structure formed on the semiconductor substrate of the third region to expose the semiconductor substrate; and
forming a source contact coupled with the exposed semiconductor substrate and extending vertically from the surface of the semiconductor substrate.
19. The method of claim 16 , further comprising:
removing the hard mask patterns formed in the first region; and
forming a data storage unit in a space from which each hard mask pattern is removed.