Low-power level-shift circuit for data-dependent signals

1. A low-power level-shift circuit for data-dependent signals, the circuit comprising:

a buffer circuit biased by a low-voltage domain voltage supply and configured to receive a data-dependent signal;

a coupling capacitor coupled, at a first node, to an output node of the buffer circuit; and

a biasing circuit coupled to a second node of the coupling capacitor that is directly coupled to a switch,

wherein the level-shift circuit is configured to translate a voltage level of the received data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch.

2. The circuit of claim 1 , wherein the switch comprises a DAC switch, wherein the DAC switch comprises a PMOS switch, wherein the level-shift circuit is configured to allow use of thin-oxide PMOS switch for the DAC switch, and wherein the DAC switch is biased using a high-voltage domain supply voltage.

3. The circuit of claim 1 , wherein the data-dependent signal comprises a digital signal, wherein the digital signal comprises a low-voltage domain return-to-zero signal, and wherein the low-voltage domain comprises a voltage range approximately between 0.8 and 1.2 volt.

4. The circuit of claim 3 , wherein the biasing circuit is controlled by a clock signal that is synchronized with the data-dependent signal.

5. The circuit of claim 1 , wherein the biasing circuit is configured to provide a voltage level at the second node of the coupling capacitor, and wherein the voltage level is controlled by a clock signal, and wherein the voltage level tracks an average voltage level of the data-dependent signal.

6. The circuit of claim 1 , wherein the high-voltage domain comprises a voltage range approximately between two and six volts.

7. The circuit of claim 1 , wherein the biasing circuit comprises a voltage divider coupled to a PMOS transistor and a small coupling capacitor, and wherein the PMOS transistor is a fast thin-oxide PMOS transistor.

8. The circuit of claim 7 , wherein the PMOS transistor provides a high voltage at the second node of the coupling capacitor when the data-dependent signal is one.

9. A method for providing a low-power level-shift circuit for data-dependent signals, the method comprising:

configuring a buffer circuit to be biased by a low-voltage domain voltage supply and configuring the buffer circuit to receive a data-dependent signal;

coupling a coupling capacitor, at a first node, to an output node of the buffer circuit;

coupling a biasing circuit to a second node of the coupling capacitor that is directly coupled to a switch; and

configuring the level-shift circuit to translate a voltage level of the received data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch.

10. The method of claim 9 , wherein the switch comprises a DAC switch, wherein the DAC switch comprises a PMOS switch.

11. The method of claim 10 , further comprising configuring the level-shift circuit to allow use of a thin-oxide PMOS switch for the DAC switch, and wherein the DAC switch is biased by using a high-voltage domain supply voltage.

12. The method of claim 9 , further comprising controlling the biasing circuit by a clock signal that is synchronized with the data-dependent signal.

13. The method of claim 9 , further comprising configuring the biasing circuit to provide a voltage level at the second node of the coupling capacitor; and controlling the voltage level by a clock signal.

14. The method of claim 13 , further comprising configuring the biasing circuit to provide the voltage level that tracks an average voltage level of the data-dependent signal.

15. The method of claim 9 , wherein the biasing circuit comprises a voltage divider coupled to a PMOS transistor and a small coupling capacitor, and wherein the PMOS transistor is a fast thin-oxide PMOS transistor.

16. The method of claim 15 , wherein the PMOS transistor provides a high voltage at the second node of the coupling capacitor when the data-dependent signal is one.

17. A communication device, comprising:

a digital-to-analog converter (DAC) circuit configured to convert an analog signal to a digital signal, the DAC circuit including a switch;

a level-shift circuit configured to translate a voltage level of a data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch, the level-shift circuit comprising:

a buffer circuit biased by a low-voltage domain voltage supply and configured to receive the data-dependent signal;

a coupling capacitor coupled, at a first node, to an output node of the buffer circuit; and

a biasing circuit coupled to a second node of the coupling capacitor that is directly coupled to the switch.

18. The communication device of claim 17 , wherein the switch comprises a DAC switch, wherein the DAC switch comprises a PMOS switch, wherein the level-shift circuit is configured to allow use of thin-oxide PMOS switch for the DAC switch, and wherein the DAC switch is biased using a high-voltage domain supply voltage.

19. The communication device of claim 17 , wherein the data-dependent signal comprises a digital signal, wherein the digital signal comprises a low-voltage domain return-to-zero signal, and wherein the low-voltage domain comprises a voltage range approximately between 0.8 and 1.2 volt.

20. The communication device of claim 17 , wherein:

the biasing circuit is controlled by a clock signal that is synchronized with the data-dependent signal,

the biasing circuit is configured to provide a voltage level at the second node of the coupling capacitor,

the voltage level is controlled by a clock signal,

the voltage level tracks an average voltage level of the data-dependent signal,

the biasing circuit comprises a voltage divider coupled to a PMOS transistor and a small coupling capacitor,

the PMOS transistor is a fast thin-oxide PMOS transistor, and

the PMOS transistor provides a high voltage at the second node of the coupling capacitor when the data-dependent signal is one.