Kernel masking of DRAM defects
Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.
1. A method for kernel masking dynamic random access memory (DRAM) defects, the method comprising:
detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM);
receiving error data associated with the physical address from the DRAM;
storing the received error data in a failed address table located in a non-volatile memory; and
retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold;
wherein the retiring the kernel page corresponding to the physical address comprises:
generating and storing a bad pages list in the non-volatile memory, the bad pages list identifying a kernel page holding the physical address which is to be excluded from memory allocation.
2. The method of claim 1 , wherein the single-bit error is detected and corrected by the DRAM.
3. The method of claim 1 , wherein receiving the error data associated with the physical address from the DRAM comprises: an operating system querying the DRAM for error data.
4. The method of claim 1 , wherein the received error data identifies a DRAM bank, column, and row address corresponding to a failed codeword address.
5. The method of claim 4 , wherein the storing the received error data in the failed address table comprises: updating the number of errors associated with the failed codeword address.
6. The method of claim 1 , further comprising:
transferring content of the kernel page to a new empty kernel page; and
removing the kernel page from future use.
7. The method of claim 1 , further comprising:
at a device boot-up, reading the bad pages list stored in the non-volatile memory; and
excluding the kernel page identified in the bad pages list from an operating system free page block list.
8. The method of claim 1 , further comprising:
executing, at a device boot-up, a primary boot loader from a memory other than the DRAM and the non-volatile memory;
reading the bad pages list from the non-volatile memory; and
determining a contiguous block of error-free DRAM by excluding one or more kernel pages identified in the bad pages list.
9. The method of claim 8 , further comprising:
executing a secondary boot loader from the error-free DRAM;
loading an operating system from the error-free DRAM;
the operating system configuring a free blocks list that excludes the kernel page identified in the bad pages list.
10. The method of claim 1 , wherein the retiring the kernel page corresponding to the physical address comprises: excluding the kernel page from allocated DRAM.
11. A system for kernel masking dynamic random access memory (DRAM) defects, the system comprising:
means for detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM);
means for receiving error data associated with the physical address from the DRAM;
means for storing the received error data in a failed address table located in a non-volatile memory; and
means for retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold, wherein the means for retiring the kernel page corresponding to the physical address comprises:
means for generating and storing a bad pages list in the non-volatile memory, the bad pages list identifying a kernel page holding the physical address which is to be excluded from memory allocation.
12. The system of claim 11 , wherein the means for receiving the error data from the DRAM comprises: means for querying the DRAM for error data.
13. The system of claim 11 , wherein the received error data identifies a DRAM bank, column, and row address corresponding to a failed codeword address.
14. The system of claim 13 , wherein the means for storing the received error data in the failed address table comprises: means for updating the number of errors associated with the failed codeword address.
15. The system of claim 11 , further comprising:
means for reading, at a device boot-up, the bad pages list stored in the non-volatile memory; and
means for excluding the kernel page identified in the bad pages list from an operating system free page block list.
16. The system of claim 11 , further comprising:
means for executing, at a device boot-up, a primary boot loader from a memory other than the DRAM and the non-volatile memory;
means for reading the bad pages list from the non-volatile memory; and
means for determining a contiguous block of error-free DRAM by excluding one or more kernel pages identified in the bad pages list.
17. The system of claim 11 , further comprising:
means for executing a secondary boot loader from the error-free DRAM;
means for loading an operating system from the error-free DRAM;
means for configuring an operating system free blocks list that excludes the kernel page identified in the bad pages list.
18. The system of claim 11 , wherein the retiring the kernel page corresponding to the physical address comprises: excluding the kernel page from allocated DRAM.
19. A computer program embodied in a non-transitory computer readable medium and executable by a processor for kernel masking dynamic random access memory (DRAM) defects, the computer program comprising logic configured to:
detect and correct a single-bit error associated with a physical address in a dynamic random access memory (DRAM);
receive error data associated with the physical address from the DRAM;
store the received error data in a failed address table located in a non-volatile memory; and
retire a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold, wherein the logic configured to retire the kernel page corresponding to the physical address comprises: logic configured to generate and store a bad pages list in the non-volatile memory, the bad pages list identifying a kernel page holding the physical address which is to be excluded from memory allocation.
20. The computer program of claim 19 , wherein the single-bit error is detected and corrected by the DRAM.
21. The computer program of claim 19 , wherein the logic configured to receive the error data from the DRAM comprises: logic configured to query the DRAM for error data.
22. The computer program of claim 19 , wherein the received error data identifies a DRAM bank, column, and row address corresponding to a failed codeword address.
23. The computer program of claim 22 , wherein the logic configured to store the received error data in the failed address table comprises: logic configured to update the number of errors associated with the failed codeword address.
24. The computer program of claim 19 , further comprising:
logic configured to read, at a device boot-up, the bad pages list stored in the non-volatile memory; and
logic configured to exclude the kernel page identified in the bad pages list from an operating system free page block list.
25. The computer program of claim 19 , further comprising:
logic configured to execute, at a device boot-up, a primary boot loader from a memory other than the DRAM and the non-volatile memory;
logic configured to read the bad pages list from the non-volatile memory; and
logic configured to identify a contiguous block of error-free DRAM by excluding one or more kernel pages identified in the bad pages list.
26. The computer program of claim 25 , further comprising:
logic configured to execute a secondary boot loader from the error-free DRAM;
logic configured to load an operating system from the error-free DRAM;
logic configured to generate a free blocks list that excludes the kernel page identified in the bad pages list.
27. The computer program of claim 19 , wherein the logic configured to retire the kernel page corresponding to the physical address comprises: logic configured to exclude the kernel page from allocated DRAM.
28. A system for masking dynamic random access memory (DRAM) defects, the system comprising:
a dynamic random access memory (DRAM) system;
an error correcting code (ECC) module for detecting and correcting bit errors associated with failed codeword addresses in the DRAM system; and
a central processing unit (CPU) executing an operating system comprising a bad page masking module, the bad page masking module comprising logic configured to:
receive, via one or more of the DRAM system and the ECC module, error data associated with the failed codeword addresses;
store the received error data in a failed codeword address table located in a non-volatile memory; and
retire kernel pages corresponding to a failed codeword address if a number of errors associated with a respective failed codeword address exceeds an error count threshold, wherein the logic configured to retire the kernel page corresponding to the failed codeword address comprises: logic configured to generate and store a bad pages list in the non-volatile memory, the bad pages list identifying a kernel page holding the failed codeword address.
29. The system of claim 28 , wherein the ECC module resides in the DRAM system, and the CPU resides on a system on chip (SoC) electrically coupled to the DRAM system.
30. The system of claim 28 , wherein the logic configured to receive, via one or more of the DRAM system and the ECC module, the error data comprises: logic configured to query the DRAM system for error data.
31. The system of claim 28 , wherein the logic configured to store the received error data in the failed codeword address table comprises: logic configured to update the number of errors associated with a failed codeword address.
32. The system of claim 28 , further comprising:
logic configured to read, at a device boot-up, the bad pages list stored in the non-volatile memory; and
logic configured to exclude the kernel page identified in the bad pages list from an operating system free page block list.
33. The system of claim 28 , further comprising:
logic configured to execute, at a device boot-up, a primary boot loader from one of a read only memory (ROM) and a static random access memory (SRAM);
logic configured to read the bad pages list from the non-volatile memory; and
logic configured to identify a contiguous block of error-free DRAM by excluding the kernel pages identified in the bad pages list.
34. The system of claim 33 , further comprising:
logic configured to execute a secondary boot loader from the error-free DRAM;
logic configured to load an operating system from the error-free DRAM;
logic configured to generate a free blocks list that excludes the kernel page identified in the bad pages list.
35. The system of claim 28 , wherein the logic configured to retire the kernel pages corresponding to the respective failed codeword addresses comprises: logic configured to exclude the kernel pages identified in the bad pages list from allocated DRAM.
36. The system of claim 28 , embodied in a portable computing device.