Memory subsystem with wrapped-to-continuous read

1. A computer implemented method for accessing data, comprising:

receiving two or more requests for data stored across at least a first memory area and a second memory area of a memory, wherein the two or more requests for data are received from a CPU of a host;

responsive to determining that the first memory area is adjacent to the second memory area, merging the received two or more requests for data into a single request for data across at least the first memory area and the second memory area, and updating a read length associated with the single request such that the updated read length encompasses at least the first memory area and the second memory area;

performing, by at least one processor, a wrapped read of data within the first memory area of the memory;

performing, by the at least one processor responsive to the single request and using the updated read length, a continuous read of data within the second memory area of the memory, the second memory area being adjacent to the first memory area, wherein the continuous read starts at a first boundary of the second memory area, and is performed automatically after reading a final address of the wrapped read of data within the first memory area; and

controlling a timing of the performing of the wrapped read and a timing of the performing of the continuous read using a state machine coupled to the at least one processor.

2. The computer implemented method of claim 1 , further comprising:

continuing the continuous read of data within one or more additional adjacent memory areas of the memory, wherein the continuous read of data within one of the one or more additional adjacent memory areas occurs automatically after the continuous read of data within a previous adjacent memory area.

3. The computer implemented method of claim 1 , further comprising:

determining if the requested data is stored across a plurality of adjacent memory areas of the memory.

4. The computer implemented method of claim 1 , wherein the receiving comprises receiving the two or more requests for data from a cache memory controller.

5. The computer implemented method of claim 4 , further comprising transmitting, by the at least one processor, at least the requested data to the cache memory controller.

6. The computer implemented method of claim 5 , wherein the data within the first memory area is written to a first cacheline of a cache associated with the cache memory controller and the data within the second memory area is written to a second cacheline of the cache.

7. A system comprising:

a plurality of memory devices;

a memory controller comprising

a decoder configured to receive two or more requests for data stored across at least a first memory area and a second memory area of the plurality of memory devices, wherein the two or more requests for data are received from a CPU of a host;

a merge detect module configured to determine that the first memory area is adjacent to the second memory area and responsively merge the received two or more requests for data into a single request for data across at least the first memory area and the second memory area, and update a read length associated with the single request such that the updated read length encompasses at least the first memory area and the second memory area;

a processor configured to:

perform a wrapped read of data within the first memory area, and

responsive to the single request and using the updated read length, perform a continuous read of data within the second memory area, wherein the continuous read starts at a first boundary of the second memory area; wherein after reading a final address of the wrapped read of data within the first memory area, the processor automatically starts the continuous read of data at a first boundary of the second memory area.

8. The system of claim 7 , wherein the processor is further configured to perform a continuous read of data within one or more additional adjacent memory areas.

9. The system of claim 7 , wherein the memory controller is configured to receive the two or more requests for data from a cache memory controller.

10. The system of claim 9 , wherein the memory controller is further configured to transmit at least the requested data to the cache memory controller.

11. The system of claim 10 , wherein the cache memory controller is configured to write the data within the first memory area to a first cacheline of a cache and to write the data within the second memory area to a second cacheline of the cache.

12. The system of claim 7 , wherein the memory controller further comprises a counter configured to count down a length of the read length.

13. A tangible computer-readable device having instructions stored upon that, when executed by at least one computing device, causes the at least one computing device to perform operations comprising:

receiving two or more requests for data stored across at least a first memory area and a second memory area of a memory, wherein the two or more requests for data are received from a CPU of a host;

merging the received two or more requests for data into a single request for data across at least the first memory area and the second memory area, and updating a read length such that the updated read length encompasses at least the first memory area and the second memory area;

based on the single request,

performing a wrapped read of data within the first memory area of the memory; and

performing a continuous read of data within the second memory area of the memory using the updated read length, the second memory area being adjacent to the first memory area, wherein the continuous read starts at a first boundary of the second memory area, and is performed automatically after reading a final address of the wrapped read of data within the first memory area; and

controlling a timing of the performing of the wrapped read and a timing of the performing of the continuous read using a state machine.