Thin form factor computational array cameras and modular array cameras

1. An X×Y sub-array module comprising:

an X×Y arrangement of focal planes, wherein:

X and Y are each greater than or equal to 1;

each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels;

each focal plane does not include pixels from another focal plane; and

the X×Y arrangement of focal planes are embodied within an integrated circuit that does not include any focal planes of another X×Y sub-array module; and

an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, each of which being configured to independently capture an image of a scene, wherein each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene;

image data output circuitry that is configured to output image data from the X×Y sub-array module that is capable of being aggregated with image data from other sub-array modules to construct so that an image of the scene; and

interface circuitry configured to couple, either directly or indirectly, with one of:

another X×Y sub-array module or a processor that is in electrical communication with at least one other X×Y sub-array module;

wherein the interface circuitry is configured to transmit output image data to a directly or indirectly coupled X×Y sub-array module or a directly or indirectly coupled processor that is in electrical communication with at least one other X×Y sub-array module.

2. The X×Y sub-array module of claim 1 , wherein X is 1.

3. The X×Y sub-array module of claim 1 , wherein X and Y are each greater than 1.

4. The X×Y sub-array module of claim 1 , wherein the arrangement of cameras are embodied within a single monolithic structure.

5. An M×N array camera comprising:

a plurality of X×Y sub-array modules, each comprising:

an X×Y arrangement of focal planes, wherein:

X and Y are each greater than or equal to 1;

each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels; and

each focal plane does not include pixels from another focal plane;

the X×Y arrangement of focal planes are embodied within an integrated circuit that does not include any focal planes of another X×Y sub-array module; and

an X×Y arrangement of lens stacks, the X×Y arrangement of lens stacks being disposed relative to the X×Y arrangement of focal planes so as to form an X×Y arrangement of cameras, each of which being configured to independently capture an image of a scene, wherein each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene;

image data output circuitry that is configured to output image data from the sub-array module that is capable of being aggregated with image data from other sub-array modules to construct an image of the scene; and

interface circuitry configured to couple, either directly or indirectly, with one of: another X×Y sub-array module or a processor that is in electrical communication with at least one other X×Y sub-array module;

wherein the interface circuitry is configured to transmit output image data to a directly or indirectly coupled X×Y sub-array module or a directly or indirectly coupled processor that is in electrical communication with at least one other X×Y sub-array module;

wherein the plurality of X×Y sub-array modules define at least some of the cameras in an M×N arrangement of cameras; and

a processor;

wherein each sub-array module is configured to transmit respective output image data to the processor via its respective distinct interface circuitry;

wherein the processor is configured to construct an image of the scene using image data generated by each of the sub-array modules.

6. The array camera of claim 5 , wherein X is 1 and M is 1.

7. The array camera of claim 5 , wherein the plurality of X×Y sub-array modules define an M×N arrangement of cameras.

8. The array camera of claim 5 , further comprising circuitry that aggregates the image data generated by each of the sub-array modules into a single MIPI output, and provides the MIPI output to the processor.

9. The array camera of claim 5 , further comprising a parallax disparity resolution module, wherein the parallax disparity resolution module is configured to receive image data captured by each sub-array module, implement a parallax detection and correction process on the received image data, and output the result for further processing.

10. The array camera of claim 9 , further comprising circuitry that converts the output of the parallax disparity resolution module into a single MIPI output, and provides the MIPI output to the processor.

11. The array camera of claim 10 , wherein the parallax disparity resolution module comprises a processor and memory, wherein the memory contains software to configure the processor to act as a parallax disparity resolution module.

12. The array camera of claim 10 , wherein the parallax disparity resolution module is a hardware parallax disparity resolution module.

13. The array camera of claim 5 , wherein M and N are each greater than or equal to 2.

14. The array camera of claim 5 , wherein at least two of the plurality of sub-array modules are adjoined to the interconnects of a single substrate, and are each capable of outputting image data through the interconnects.

15. The array camera of claim 14 , wherein each of the plurality of sub-array modules are adjoined to the interconnects of a single substrate, and are each capable of outputting image data through the interconnects.

16. The array camera of claim 15 , wherein the substrate is optically transparent.

17. The array camera of claim 16 , wherein the substrate is glass.

18. The array camera of claim 15 , wherein the substrate is ceramic with through-holes that clear the optical path.

19. The array camera of claim 5 , wherein at least one sub-array module is embodied within a single monolithic structure.

20. The array camera of claim 5 , wherein each sub-array module is embodied within a single respective monolithic structure.

21. The array camera of claim 5 , further comprising:

a plurality of I/O devices, wherein each of the plurality of I/O devices interfaces with at least one camera: and

a separate I/O block that includes circuitry configured to receive image data, aggregate the received image data, and output the aggregated image data to the processor; and

wherein each of the plurality of I/O devices interfaces with the I/O block.

22. The array camera of claim 21 , wherein the number of I/O devices equals the number of sub-array modules, and wherein each I/O device interfaces with a corresponding sub-array module.

23. The X×Y sub-array module of claim 1 , wherein the interface circuitry is configured to transmit output image data to a directly or indirectly coupled X×Y sub-array module.

24. The X×Y sub-array module of claim 1 , wherein the interface circuitry is configured to transmit output image data to a directly or indirectly coupled processor that is in electrical communication with at least one other X×Y sub-array module.

25. The M×N array camera of claim 5 , wherein at least one X×Y sub-array module comprises interface circuitry configured to transmit output image data to a directly or indirectly coupled X×Y sub-array module.

26. The M×N array camera of claim 5 , wherein at least one X×Y sub-array module comprises interface circuitry configured to transmit output image data to a directly or indirectly coupled X×Y processor that is in electrical communication with at least one sub-array module.