Parasitic capacitance cancellation in capacitive measurement
An integrated circuit compensates for parasitic capacitance in a capacitive measuring apparatus wherein a capacitance measurement is done by repeatedly transferring charge from a capacitor to be measured to a reference capacitor.
1. An integrated circuit for measuring capacitance of a capacitive structure using a charge transfer technique, said circuit comprising means for transferring charge during each of a plurality of cycles during a capacitive measurement to a reference capacitor wherein the charge transferred from the measured capacitive structure and accumulated in the reference capacitor during every cycle in the capacitive measurement is reduced by a predetermined amount of charge, and wherein the charge transferred for measurement is scaled using a current mirror structure.
2. The integrated circuit of claim 1 , wherein the current mirror structure includes a selection of scaling ratios that can be selected in accordance with an algorithm to optimize the capacitive measurement for a specific parameter.
3. The integrated circuit of claim 2 , where said parameter is the stability of the measurement.
4. The integrated circuit of claim 1 wherein the reference capacitor is located on-chip in the integrated circuit.
5. The integrated circuit of claim 1 further including a number of selectable on-chip capacitors, and wherein the selection of said on-chip capacitors determines the amount of charge reduction during every cycle.
6. The integrated circuit of claim 1 , wherein said amount of charge reduction is selected according to an algorithm which optimizes the capacitive measurement for a specific parameter.
7. The integrated circuit of claim 6 , where said parameter is the sensitivity of the measurement.
8. The integrated circuit of claim 6 , where said parameter is the speed of the measurement.
9. The integrated circuit of claim 6 , where said parameter is the stability of the measurement.
10. The integrated circuit of claim 2 , where said parameter is the speed of the measurement.
11. The integrated circuit of claim 2 , where said parameter is the sensitivity of the measurement.
12. An integrated circuit for measuring capacitance of a capacitive structure using a charge transfer technique, said circuit comprising means for transferring charge during each of a plurality of cycles during a capacitive measurement to a reference capacitor wherein the charge transferred from the measured capacitive structure and accumulated in the reference capacitor during every cycle in the capacitive measurement is reduced by a predetermined amount of charge; and, wherein said integrated circuit further comprises a current mirror structure for scaling the amount of charge reduction during every cycle.
13. The integrated circuit of claim 12 , wherein the reduction of charge is independent of the voltage across said reference capacitor.
14. The integrated circuit of claim 12 , wherein the current mirror structure includes a selection of scaling ratios that can be selected in accordance with an algorithm to optimize the capacitive measurement for a specific parameter.
15. The integrated circuit of claim 14 , where said parameter is the sensitivity of the measurement.
16. The integrated circuit of claim 14 , where said parameter is the speed of the measurement.
17. The integrated circuit of claim 14 , where said parameter is the stability of the measurement.