Operational amplifier circuit
View Patent ↗Provided is an operational amplifier circuit capable of operating with lower current consumption. An amplifier stage, a FIR filter, and a sample and hold circuit are connected in series, thus enabling reduction of an input offset voltage and amplification of an input signal voltage without using an integral circuit. Current consumption of the operational amplifier circuit is reduced because the integral circuit is not used.
1. An operational amplifier circuit for amplifying a signal input to input terminals and outputting the amplified signal to an output terminal, the operational amplifier circuit comprising:
a first amplifier stage connected to the input terminals of the operational amplifier circuit;
a chopping circuit connected to the input terminals of the operational amplifier circuit, the chopping circuit being controlled by a first clock and having a function of modulating the input signal;
a second amplifier stage connected to output terminals of the chopping circuit;
a filter connected to output terminals of the second amplifier stage that is configured to add a signal output from the second amplifier to a delayed version of the signal so that the filter has a finite impulse response (FIR) characteristic;
a sample and hold circuit connected to the FIR filter, the sample and hold circuit being controlled by a second clock that is synchronized with the first clock;
a third amplifier stage connected to output terminals of the sample and hold circuit; and
a fourth amplifier stage connected to an output terminal of the first amplifier stage and an output terminal of the third amplifier stage, the fourth amplifier stage including an output terminal connected to the output terminal of the operational amplifier circuit.
2. An operational amplifier circuit according to claim 1 , wherein the FIR filter comprises:
a first weighting circuit connected to input terminals of the FIR filter and having a predetermined amplification factor;
a delay circuit connected to the input terminals of the FIR filter and having a function of outputting the input signal with a predetermined delay period;
a second weighting circuit connected to output terminals of the delay circuit and having a predetermined amplification factor; and
an adder circuit connected to an output terminal of the first weighting circuit and an output terminal of the second weighting circuit and having a function of adding input signals.