IP Library Granted Patent US 9,236,331
Granted Patent B2
US 9,236,331 · App. 14/189,609 · Granted Jan 12, 2016

Multiple die lead frame

Inventors: William E. Edwards (Ann Arbor, MI); Gary C. Johnson (Tempe, AZ)
Assignee: Freescale Semiconductor, Inc.
H01L23/49503H01L23/49541H01L23/49575H01L2224/05554H01L2224/48247
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Quick Facts
Patent No.
US 9,236,331
App. No.
14/189,609
Granted
Jan 12, 2016
Kind
B2
Abstract

An electronic apparatus includes a packaging enclosure, first and second die pads disposed within the packaging enclosure, first and second semiconductor die disposed on the first and second die pads, respectively, a plurality of packaging leads, each packaging lead projecting outward from the packaging enclosure, a plurality of packaging posts disposed within the packaging enclosure and extending inward from opposite sides of the packaging enclosure between the first and second die pads, each packaging post being connected with a respective one of the plurality of packaging leads, and a plurality of wire bonds disposed within the packaging enclosure. Each packaging post of the plurality of packaging posts is connected via a first wire bond of the plurality of wire bonds to the first semiconductor die and via a second wire bond of the plurality of wire bonds to the second semiconductor die. The plurality of packaging posts includes first and second sets of packaging posts extending inward from first and second opposite sides of the packaging enclosure, respectively.

Claims (49)

1. An electronic apparatus comprising:

a packaging enclosure;

first and second die pads disposed within the packaging enclosure;

first and second semiconductor die disposed on the first and second die pads, respectively;

a plurality of packaging leads, each packaging lead projecting outward from the packaging enclosure;

a plurality of packaging posts disposed within the packaging enclosure and extending inward between the first and second die pads, each packaging post being connected with a respective one of the plurality of packaging leads; and

a plurality of wire bonds disposed within the packaging enclosure;

wherein each packaging post of the plurality of packaging posts is connected via a first respective wire bond of the plurality of wire bonds to the first semiconductor die and via a second respective wire bond of the plurality of wire bonds to the second semiconductor die; and

wherein the plurality of packaging posts comprises first and second sets of packaging posts extending inward from first and second opposite sides of the packaging enclosure, respectively.

2. The electronic apparatus of claim 1 , wherein each packaging post extends laterally across a midline that bisects the first and second semiconductor die.

3. The electronic apparatus of claim 1 , wherein:

each packaging post is connected to a respective first bond pad of a plurality of first bond pads on the first semiconductor die;

each packaging post is connected to a respective second bond pad of a plurality of second bond pads on the second semiconductor die; and

each packaging post extends laterally across a line that intersects the respective first bond pad and the respective second bond pad.

4. The electronic apparatus of claim 1 , further comprising a connecting bar that extends between the first and second die pads to connect the first and second die pads to one another.

5. The electronic apparatus of claim 4 , wherein the connecting bar has a serpentine shape.

6. The electronic apparatus of claim 1 , further comprising a plurality of unshared packaging leads, the plurality of unshared packaging leads comprising first and second tie bars connected to the first and second die pads, respectively.

7. The electronic apparatus of claim 1 , further comprising a plurality of unshared packaging leads, wherein each unshared packaging lead is electrically coupled to a respective bond pad of one of the first and second semiconductor die.

8. The electronic apparatus of claim 1 , wherein:

the first and second semiconductor die have layouts that are identical; and

the layouts of the first and second semiconductor die are oriented 180 degrees relative to one another.

9. The electronic apparatus of claim 1 , wherein:

each of the first and second semiconductor die comprises a respective set of bond pads to which the plurality of wire bonds are connected; and

the bond pads of the first semiconductor die are disposed on a side of the first semiconductor die that faces a side of the second semiconductor die on which the bond pads of the second semiconductor die are disposed.

10. The electronic apparatus of claim 1 , wherein the first and second semiconductor die are configured such that first and second packaging leads of the plurality of packaging leads are configured to provide a shared ground and a shared power supply for the first and second semiconductor die.

11. The electronic apparatus of claim 1 , wherein the first and second semiconductor die are configured such that a respective packaging lead of the plurality of packaging leads is configured to provide a shared serial parallel interface for the first and second semiconductor die.

12. An electronic apparatus comprising:

a packaging enclosure;

first and second semiconductor die disposed within the packaging enclosure;

a lead frame comprising:

first and second die pads disposed within the packaging enclosure and on which the first and second semiconductor die are disposed, respectively;

a plurality of pins projecting outward from the packaging enclosure; and

a plurality of interconnects disposed within the packaging enclosure and extending inward between the first and second die pads, each interconnect being connected with a respective one of the plurality of pins; and

a plurality of wire bonds disposed within the packaging enclosure;

wherein each interconnect of the plurality of interconnects is connected via a first respective wire bond of the plurality of wire bonds to the first semiconductor die and via a second respective wire bond of the plurality of wire bonds to the second semiconductor die; and

wherein the plurality of interconnects comprises first and second sets of interconnects extending inward from first and second opposite sides of the packaging enclosure, respectively.

13. The electronic apparatus of claim 12 , wherein:

each interconnect extends laterally across a line that intersects bond pads on the first and second semiconductor die to which the interconnect is connected;

the plurality of pins are disposed along first and second sides of the packaging enclosure that oppose one another; and

first and second sets of the plurality of interconnects extend from the pins along the first and second sides, respectively.

14. The electronic apparatus of claim 13 , wherein the lead frame further comprises a connecting bar that extends across the midline between the first and second die pads to connect the first and second die pads to one another.

15. The electronic apparatus of claim 12 , wherein the lead frame further comprises a plurality of unshared pins, the plurality of unshared pins comprising first and second tie bars connected to the first and second die pads, respectively.

16. The electronic apparatus of claim 12 , wherein:

the first and second semiconductor die have layouts that are identical; and

the layouts of the first and second semiconductor die are oriented 180 degrees relative to one another.

17. The electronic apparatus of claim 1 , wherein each packaging post is in contact with a respective one of the plurality of packaging leads.

18. The electronic apparatus of claim 12 , wherein each interconnect is in contact with a respective one of the plurality of pins.

19. The electronic apparatus of claim 1 , wherein the packaging posts extending from a respective side of the first and second opposite sides are disposed in parallel.

20. The electronic apparatus of claim 4 , wherein the connecting bar comprises a central portion oriented in parallel with the plurality of packaging posts.

Assignments (26)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBERS PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0438. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0136 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBERS 12222918, 14185362, 14147598, 14185868 & 14196276 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0479. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0498 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0479 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0438 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0763 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 032845/0497 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0522 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2014
From: EDWARDS, WILLIAM E.; JOHNSON, GARY C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 032295/0434 →
Continuity (1)
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