IP Library Granted Patent US 9,324,442
Granted Patent B2
US 9,324,442 · App. 14/189,962 · Granted Apr 26, 2016

Semiconductor memory device

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Quick Facts
Patent No.
US 9,324,442
App. No.
14/189,962
Granted
Apr 26, 2016
Kind
B2
Abstract

A semiconductor memory device includes a memory cell, a sense amplifier electrically connected to the memory cell, the sense amplifier including a node for sensing a voltage during a sense operation and a data latch electrically connected to the node and configured to hold a first voltage corresponding to a voltage of the node when a strobe signal is issued during a strobe operation, and a controller configured to raise the voltage of the node during the strobe operation before the strobe signal is issued.

Claims (29)

1. A semiconductor memory device comprising:

a memory cell;

a sense amplifier electrically connected to the memory cell, the sense amplifier including a node for sensing a voltage during a sense operation and a data latch electrically connected to the node and configured to hold a first voltage corresponding to a voltage of the node when a strobe signal is issued during a strobe operation; and

a controller that includes a sense node driver that is electrically connected to the node through a capacitor and is configured to raise the voltage of the node during the strobe operation before the strobe signal is issued,

wherein an output voltage of the sense node driver is increased to a first level from an initial level at the start of the sense operation and then returned to the initial level at the end of the sense operation.

2. The device according to claim 1 , wherein the controller raises the voltage of the node by a first amount at the start of the sense operation and by a second amount during the strobe operation before the strobe signal is issued.

3. The device according to claim 2 , wherein the second amount is smaller than the first amount.

4. The device according to claim 3 , wherein the memory cell is one of a plurality of memory cells of a memory array in which word lines are each connected to a plurality of memory cells across different memory string groups, and the second amount is substantially equal to a decrease in the voltage at the node caused by leakage currents.

5. The device according to claim 3 , further comprising a temperature sensor, wherein the controller is configured to determine the first and second amounts according to a temperature detected by the temperature sensor.

6. The device according to claim 1 , wherein the output voltage of the sense node driver is increased to a second level that is lower than the first level from an initial level during the strobe operation before the strobe signal is issued and maintained at the second level until the end of the strobe operation.

7. The device according to claim 6 , wherein the memory cell is one of a plurality of memory cells of a memory array in which word lines are each connected to a plurality of memory cells across different memory string groups, and the second amount is substantially equal to a decrease in the voltage at the node caused by leakage currents.

8. The device according to claim 6 , further comprising a temperature sensor, wherein the controller is configured to determine the first and second levels according to a temperature detected by the temperature sensor.

9. A semiconductor memory device comprising:

a memory cell array including a plurality of memory string groups, each of the memory string groups including a plurality of memory cells connected to different bit lines and a common source line;

word lines each connected to a plurality of memory cells across different memory string groups;

a sense amplifier electrically connected to a selected memory cell, the sense amplifier including a node for sensing a voltage during a sense operation and a data latch electrically connected to the node and configured to hold a first voltage corresponding to a voltage of the node when a strobe signal is issued during a strobe operation; and

a controller configured to raise the voltage of the node by an amount sufficient to compensate for a decrease in the voltage at the node caused by leakage currents through non-selected memory cells that are connected in common to a word line as the selected memory cell, wherein

the controller raises the voltage of the node during the sense operation by a first amount and during the strobe operation before the strobe signal is issued by a second amount.

10. The device according to claim 9 , wherein the second amount is smaller than the first amount.

11. The device according to claim 10 , further comprising a temperature sensor, wherein the controller is configured to determine the first and second amounts according to a temperature detected by the temperature sensor.

12. A method of reading data stored in a memory cell of a semiconductor memory device including a sense amplifier electrically connected to the memory cell, the sense amplifier including a node for sensing a voltage during a sense operation and a data latch electrically connected to the node and configured to hold a first voltage corresponding to a voltage of the node when a strobe signal is issued during a strobe operation, said method comprising:

performing a sense operation;

initiating a strobe operation after the end of the sense operation; and

during the strobe operation, increasing the voltage of the node and then issuing the strobe signal,

wherein during the sense operation, the voltage of the node is increased, the amount of voltage increase during the sense operation being larger than the amount of voltage increase during the strobe operation before the strobe signal is issued.

13. The method of claim 12 , further comprising:

sensing a temperature in the semiconductor memory device by a temperature sensor; and

determining the amounts of the voltage increases according to the temperature detected by the temperature sensor.

14. The method of claim 12 , wherein the memory cell is one of a plurality of memory cells of a memory array in which word lines are each connected to a plurality of memory cells across different memory string groups, and the amount of voltage increase is substantially equal to a decrease in the voltage at the node caused by leakage currents.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2014
From: MAEJIMA, HIROSHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 032297/0212 →