Semiconductor apparatus and reduced current and power consumption
View Patent ↗A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.
1. A semiconductor apparatus comprising:
a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal;
a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and
a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.
2. The semiconductor apparatus according to claim 1 , wherein the mode control circuit comprises:
a control signal generation unit configured to output the first control signal and a second control signal in response to the power-down mode signal; and
a CML circuit unit configured to generate the differential output signals which swing in the CML area in response to the second control signal.
3. The semiconductor apparatus according to claim 2 , wherein the CML circuit unit controls a sink current in response to the second control signal.
4. The semiconductor apparatus according to claim 3 , wherein the CML circuit unit controls an amount of current applied to an output node in proportion to a controlled amount of the sink current.
5. The semiconductor apparatus according to claim 2 , wherein the control signal generation unit comprises:
a first element configured to generate the first control signal in response to an operation enable signal and an inverted signal of the power-down mode signal; and
a second element configured to generate the second control signal and an inverted signal of the second control signal in response to the power-down mode signal.