Synchronous transfer of streaming data in a distributed antenna system
View Patent ↗Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a binary encoded data stream transmitted over a communication medium. The method includes receiving a modulated signal that includes the binary encoded data stream and generating a recovered clock signal that is phase locked to the binary encoded data stream. The method further comprises generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter, while allowing the clock signal to track long-term drift.
1. A method of generating a jitter reduced clock signal from signal transmitted over a communication medium, the method comprising:
receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream;
generating a recovered clock signal that is phase locked to the binary encoded data stream with circuitry having a filter with a bandwidth that does not substantially block the long-term drift in the modulated signal; and
generating a jitter reduced clock signal by filtering the recovered clock signal using a filtering circuit having a bandwidth narrower than the bandwidth of the circuitry that is used for generating the recovered clock signal in order to remove jitter while allowing the jitter reduced clock signal to track drift of the binary encoded data stream.
2. The method of claim 1 further comprising producing at least one output clock by scaling the frequency of the jitter reduced clock signal.
3. The method of claim 1 , wherein the high speed data interface circuitry includes at least a one gigabit per second (Gbps) Ethernet interface.
4. The method of claim 3 , wherein the Ethernet interface is synchronous or asynchronous.
5. The method of claim 1 , wherein the communication medium is a communication cable having at least one twisted pair cable.
6. A distributed antenna system, comprising:
a master unit that clocks a binary encoded data stream onto high speed data interface circuitry using a modulated signal based upon an output of a reference oscillator; and
at least one remote unit that receives the modulated signal and binary encoded data stream from the master unit, the at least one remote unit including:
a clock recovery circuit that is configured to generate a recovered clock signal that is phase-locked to the binary encoded data stream and that includes a filter configured with a bandwidth that does not substantially block the long-term drift in the modulated signal; and
a filtering circuit having a bandwidth narrower than the bandwidth of the filter of the clock recovery circuit and that is configured to filter the recovered clock signal in order to remove jitter while allowing the recovered clock signal to track long-term drift of the binary encoded data stream for generating a jitter reduced clock signal.
7. The system of claim 6 further comprising a scaling circuit configured to scale the frequency of the jitter reduced clock signal to generate an output signal at a predetermined target frequency.
8. The system of claim 6 , wherein the high speed data interface circuitry is coupled to a communication medium between the master unit and at least one remote unit having at least one twisted pair cable.
9. The system of claim 6 , further comprising:
an extension unit that relays the modulated signal from the master unit to the remote unit.
10. The system of claim 6 , wherein the master unit further includes:
master unit RF transceiver circuitry for communication with a base transceiver station,
the base transceiver station providing the master unit with cellular data and the binary encoded data stream including the cellular data.
11. The system of claim 10 , the master unit RF transceiver circuitry further configured to communicate with a subscriber unit, wherein the master unit further includes:
master unit high speed data interface circuitry for communication with the at least one remote unit;
an auxiliary interface for communicating at least one of control data, maintenance data, Ethernet data, or WiFi data; and
a processor that multiplexes data from the master unit RF transceiver circuitry and the auxiliary interface for transmission to the at least one remote unit via the master unit high speed data interface circuitry, and that de-multiplexes data received from the master unit high speed data interface circuitry for transmission to the base transceiver station via the master unit RF transceiver circuitry.
12. The system of claim 6 , wherein the high speed data interface circuitry is an at least a one gigabit per second (Gbps) Ethernet interface.
13. The system of claim 6 , the remote unit further including:
high speed data interface circuitry for receiving the modulated signal from the master unit;
RF transceiver circuitry for communicating with a subscriber unit; and
a processing unit that de-multiplexes data from the remote unit high speed data interface circuitry for transmission by the RF transceiver circuitry, and that multiplexes data from the RF transceiver circuitry for transmission by the high speed data interface circuitry,
wherein the processing unit is configured adjust the rate of data being transmitted on the high speed data interface circuitry to match the capability of that interface circuitry by excluding low priority data from the multiplexed stream.
14. The system of claim 13 wherein the data that is multiplexed to the remote unit high speed data interface circuitry includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non-cellular data, control data, maintenance data, Ethernet data or WiFi data.
15. The system of claim 12 , the remote unit further including:
high speed data interface circuitry for receiving the modulated signal from the master unit;
RF transceiver circuitry for communicating cellular and non-cellular data with a subscriber unit;
an auxiliary interface for communicating at least one of control data, maintenance data, Ethernet data, or WiFi data; and
a processing unit that de-multiplexes data from the high speed data interface circuitry for transmission by the RF transceiver circuitry or the auxiliary interface, and that multiplexes data from the RF transceiver circuitry and the auxiliary interface for transmission by the high speed data interface circuitry.
16. A method of generating a jitter reduced clock signal from an encoded data stream, the method comprising:
generating a recovered clock signal that is phase locked to the binary encoded data stream with circuitry having a filter with a bandwidth that does not substantially block the long-term drift in the modulated signal;
clocking data from the encoded data stream into a processing unit based on the recovered clock signal;
with the processing unit, using the clocked data and detecting a periodic signal component, other than the bit rate, from the clocked data of the encoded data stream;
generating a reference clock signal based on the detected periodic signal component from the clocked data; and
filtering the reference clock signal with a circuit having a bandwidth narrower than the bandwidth of the circuitry used for generating the recovered clock signal and that substantially blocks jitter while substantially allowing the long-term drift of the reference clock signal.