Delamination and crack prevention in III-nitride wafers
View Patent ↗In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
1. A semiconductor wafer comprising:
a group IV substrate;
a III-Nitride body over said group IV substrate;
at least one device layer over said III-Nitride body;
grid array trenches formed in said III-Nitride body defining a plurality of III-Nitride dies in said semiconductor wafer;
each of said grid array trenches being situated between a respective one of said plurality of said III-Nitride dies and a respective sacrificial III-Nitride body, said respective sacrificail III-Nitride body being situated within a respective dicing street.
2. The semiconductor wafer of claim 1 , wherein said grid array trenches are further formed in said group IV substrate.
3. The semiconductor wafer of claim 1 , wherein said at least one device layer is a metal layer.
4. The semiconductor wafer of claim 1 , wherein said at least one device layer is a dielectric layer.
5. The semiconductor wafer of claim 1 , wherein said at least one device layer is a semiconductor layer.
6. The semiconductor wafer of claim 1 , wherein said group IV substrate is selected from the group consisting of a silicon substrate, a sapphire substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, and a separation by implantation of oxygen (SIMOX) substrate.
7. The semiconductor wafer of claim 1 , further comprising an edge trench around a perimeter of said semiconductor wafer.