PCI-E REFERENCE CLOCK PASSIVE SPLITTER AND METHOD THEREOF
A passive electronic circuit for splitting a Peripheral Component Interconnect Express (PCIe) reference clock is provided. The circuits comprises two splitting paths coupled between a clock driver and a plurality of loads, wherein each of the two splitting paths is connected, at one end through a first transmission line, to one output of a differential PCIe reference clock provided by the clock driver; wherein each of the two splitting paths includes a plurality of splitter branches, wherein each splitting branch comprises a first resistor connected in series to a second transmission line being connected in a series to a second resistor, wherein the second resistor is coupled to an input of one of the plurality of loads and the first resistor is coupled to the first transmission line through a splitting point.
1 . A passive electronic circuit for splitting a Peripheral Component Interconnect Express (PCIe) reference clock, comprising:
two splitting paths coupled between a clock driver and a plurality of loads, wherein each of the two splitting paths is connected, at one end through a first transmission line, to one output of a differential PCIe reference clock provided by the clock driver;
wherein each of the two splitting paths includes a plurality of splitter branches, wherein each splitting branch comprises a first resistor connected in series to a second transmission line being connected in a series to a second resistor, wherein the second resistor is coupled to an input of one of the plurality of loads and the first resistor is coupled to the first transmission line through a splitting point.
2 . The circuit of claim 1 , wherein the resistance value of each of the first resistor and the second resistor is a function of a number of the splitting branches and a reference impedance of the PCIe clock wire.
3 . The circuit of claim 2 , wherein the characteristic impedance of each of the first transmission line and the second transmission line is a function of a number of the splitting branches and a reference impedance of the PCIe clock wire.
4 . The circuit of claim 3 , wherein the reference load impedance is 2 pF.
5 . The circuit of claim 4 , wherein the resistance value of each of the first resistor and the second resistor is 50Ω.
6 . The circuit of claim 5 , wherein the characteristic impedance of the first transmission line and the second transmission line is 50Ω.
7 . The circuit of claim 1 , wherein the circuit is connected in a PCIe card including at least a plurality of integrated circuits (ICs) respectively coupled to the plurality of loads, each of the plurality of ICs is configured to perform a different function, wherein the circuit drives the differential reference PCIe clock to the plurality of ICs.
8 . The circuit of claim 7 , wherein the plurality of ICs includes at least a first network Wi-Fi interface compliant with the IEEE 802.11n/g standard and a second network Wi-Gig interface compliant with the IEEE 802.11ad standard.
9 . The circuit of claim 1 , wherein the PCIe card is integrated in a computing device including any one of: a laptop computer, a smartphone, a tablet computer, a personal digital assistant, a wearable computing device, a remote alarm terminal, and a kiosk.
10 . An apparatus integrated a computing device, comprising:
a slot for providing connectivity to a motherboard of the computing device;
a passive clock splitter for splitting a peripheral component interconnect Express (PCIe) reference clock;
a plurality of integrated circuits (ICs), each of the plurality of ICs is configured to perform a different function, wherein the passive clock splitter is configured to drive the differential reference PCIe clock to the plurality of ICs.
11 . The apparatus of claim 1 , wherein the passive clock splitter includes:
two splitting paths coupled between a clock driver and a plurality of loads of the plurality of ICs, wherein each of the two splitting paths is connected, at one end through a first transmission line, to one output of a differential PCIe reference clock provided by the clock driver;
wherein each of the two splitting paths includes a plurality of splitter branches, wherein each splitting branch comprises a first resistor connected in series to a second transmission line being connected in a series to a second resistor, wherein the second resistor is coupled to an input of one of the plurality of loads and the first resistor is coupled to the first transmission line through a splitting point.
12 . The apparatus of claim 11 , wherein the resistance value of each of the first resistor and the second resistor is a function of a number of the splitting branches and a reference impedance of the PCIe clock wire.
13 . The apparatus of claim 11 , wherein the characteristic impedance of each of the first transmission line and the second transmission line is a function of a number of the splitting branches and a reference impedance of the PCIe clock wire.
14 . The apparatus of claim 13 , wherein the reference load impedance is 2 pF.
15 . The apparatus of claim 14 , wherein the resistance value of each of the first resistor and the second resistor is 50Ω.
16 . The apparatus of claim 14 , wherein the characteristic impedance of the first transmission line and the second transmission line is 50Ω.
17 . The apparatus of claim 10 , wherein the plurality of ICs includes at least a first network interface and a second network interface.
18 . The apparatus of claim 17 , wherein the first network interface is a Wi-Fi interface compliant with the IEEE 802.11n/g standard and the second network interface is a Wi-Gig interface compliant with the IEEE 802.11ad standard.
19 . The apparatus of claim 10 , wherein the PCIe card is integrated in a computing device including any one of: a laptop computer, a smartphone, a tablet computer, a personal digital assistant, a wearable computing device, a remote alarm terminal, and a kiosk.