Fabrication method for microelectronic components and microchip inks used in electrostatic assembly
View Patent ↗Charge-encoded chiplets are produced using a sacrificial metal mask and associated fabrication techniques and materials that are compatible with typical semiconductor fabrication processes to provide each chiplet with two different (i.e., positive and negative) charge polarity regions generated by associated patterned charge-inducing material structures. A first charge-inducing material having a positive charge polarity is formed on a silicon wafer over previously-fabricated integrated circuits, then a sacrificial metal mask is patterned only over a portion of the charge-inducing material structure, and a second charge-inducing material structure (e.g., a self-assembling octadecyltrichlorosilane monolayer) is deposited having a negative charge polarity. The sacrificial metal mask is then removed to expose the masked portion of the first charge-inducing material structure, thereby providing the chiplet with both a positive charge polarity region and a negative charge polarity region.
1. A method for fabricating a charge-encoded microelectronic component, the method comprising:
forming a first charge-inducing material structure on an upper surface of said microelectronic component, said first charge-inducing material structure having a first surface chemistry exhibiting a first polarity;
forming a sacrificial metal mask over a first portion of said first charge-inducing material structure such that a second portion of said first charge-inducing material structure is exposed by said sacrificial metal mask;
forming a second charge-inducing material structure on the exposed second portion of said first charge-inducing material structure, said second charge-inducing material structure having a second surface chemistry exhibiting a second polarity; and
removing said sacrificial metal mask, whereby said upper surface includes a first region having the first polarity, and a second region having the second polarity,
wherein forming said first charge-inducing material structure comprises depositing a hydrophylic material, and
wherein forming said second charge-inducing material structure comprises depositing a hydrophobic material.
2. The method of claim 1 , wherein forming said first charge-inducing material structure comprises forming a layer of SiO 2 over the upper surface of said microelectronic component.
3. The method of claim 1 , wherein forming said second charge-inducing material structure comprises forming a self-assembled layer.
4. The method of claim 3 , wherein forming said self-assembled layer comprises forming a monolayer comprising a hydrophobic aliphatic material.
5. The method of claim 3 , wherein forming said self-assembled layer comprises forming a monolayer consisting of octadecyltrichlorosilane (OTS).
6. A method for fabricating a charge-encoded microelectronic component, the method comprising:
forming a first charge-inducing material structure on an upper surface of said microelectronic component, said first charge-inducing material structure having a first surface chemistry exhibiting a first polarity;
forming a sacrificial metal mask over a first portion of said first charge-inducing material structure such that a second portion of said first charge-inducing material structure is exposed by said sacrificial metal mask;
forming a second charge-inducing material structure on the exposed second portion of said first charge-inducing material structure, said second charge-inducing material structure having a second surface chemistry exhibiting a second polarity; and
removing said sacrificial metal mask, whereby said upper surface includes a first region having the first polarity, and a second region having the second polarity,
the method further comprising:
fabricating an integrated circuit on a semiconductor substrate; and
forming interconnect structures over the integrated circuit such that the interconnect structures are operably electrically connected to the integrated circuit and are disposed on said upper surface, wherein each said interconnect structure comprises one of Titanium-Tungsten (TiW) alloy or Aluminum (Al),
wherein forming said first charge-inducing material structure comprises forming a layer of SiO 2 over the upper surface, and patterning the SiO 2 layer using a buffered oxide etchant such that the interconnect structures are exposed through openings defined in the SiO 2 layer.
7. The method of claim 6 ,
wherein forming the interconnect structures comprises sputtering one of Titanium-Tungsten (TiW) alloy or Aluminum (Al), and
wherein forming the sacrificial metal mask comprises forming a layer of Molybdenum-Chromium (MoCr) alloy over a first portion of said SiO 2 layer, and then etching the MoCr alloy.
8. The method of claim 7 , wherein forming said self-assembled monolayer comprises disposing said microelectronic component in a solution containing octadecyltrichlorosilane (OTS) and tolumene.
9. The method of claim 7 ,
wherein fabricating the integrated circuit comprises utilizing a fabrication complementary metal-oxide-semiconductor (CMOS) fabrication system, and
wherein said forming the interconnect structures, forming said first charge-inducing material structure, and forming the sacrificial metal mask comprises utilizing the CMOS fabrication system.
10. A method for fabricating a charge-encoded microelectronic component, the method comprising:
forming a first charge-inducing material structure on an upper surface of said microelectronic component, said first charge-inducing material structure having a first surface chemistry exhibiting a first polarity;
forming a sacrificial metal mask over a first portion of said first charge-inducing material structure such that a second portion of said first charge-inducing material structure is exposed by said sacrificial metal mask;
forming a second charge-inducing material structure on the exposed second portion of said first charge-inducing material structure, said second charge-inducing material structure having a second surface chemistry exhibiting a second polarity; and
removing said sacrificial metal mask, whereby said upper surface includes a first region having the first polarity, and a second region having the second polarity,
the method further comprising:
fabricating an integrated circuit on a semiconductor substrate before forming said first charge-inducing material structure on said upper surface over said integrated circuit; and
after forming said sacrificial metal mask and before forming said second charge-inducing material structure:
forming a singulation etch mask over the upper surface;
bonding said semiconductor substrate to a carrier substrate using a temporary mounting adhesive;
etching through said semiconductor substrate in a peripheral region surrounding said integrated circuit; and
removing the singulation etch mask from the upper surface.
11. The method of claim 10 ,
wherein forming said singulation etch mask comprises depositing a layer comprising Nickel (Ni), and
wherein removing the singulation etch mask comprises etching the Ni layer using at least one of thiourea, sodium n-nitrobenzenesulfonate and sulfuric acid.
12. The method of claim 10 , wherein forming said second charge-inducing material structure and removing said sacrificial metal mask are performed while said substrate remains bonded to said carrier substrate.
13. The method of claim 10 , further comprising separating said substrate from said carrier substrate before forming said second charge-inducing material structure and removing said sacrificial metal mask.
14. The method of claim 13 , wherein forming said second charge-inducing material structure comprises disposing said microelectronic component in a solution containing octadecyltrichlorosilane (OTS) such that said OTS forms a coating over an entire peripheral surface of said microelectronic component.
15. A method for producing a microchip ink including a plurality of a microelectronic components, the method comprising:
fabricating a plurality of integrated circuits on a semiconductor wafer;
forming a plurality of first charge-inducing material structures on an upper surface of said semiconductor wafer such that each said first charge-inducing material structure is disposed over an associated said integrated circuit, wherein each said first charge-inducing material structure includes a first surface chemistry exhibiting a first polarity;
forming a plurality of sacrificial metal masks on the upper surface such that each said sacrificial metal mask is disposed over a first portion of an associated said first charge-inducing material structure, and such that a second portion of each said first charge-inducing material structure is exposed by said associated sacrificial metal mask;
singulating the semiconductor wafer to form said plurality of microelectronic components such that each said microelectronic component includes an associated said integrated circuit disposed on a discrete semiconductor wafer chip;
forming a plurality of second charge-inducing material structures on the upper surface of each of said plurality of microelectronic components such that each said second charge-inducing material structure is disposed on the exposed second portion of said associated first charge-inducing material structure, wherein each said second charge-inducing material structure includes a second surface chemistry exhibiting a second polarity;
removing said sacrificial metal mask, whereby said upper surface of each said integrated circuit includes a first region having the first polarity, and a second region having the second polarity; and
disposing said plurality of microelectronic components into a carrier solution.