Enabling bulk FINFET-based devices for FINFET technology with dielectric isolation
View Patent ↗A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.
1. A fin field-effect transistor (finFET) circuit, the finFET circuit comprising:
a plurality of bulk finFET devices; and
a plurality of dielectric-isolated bulk finFET devices, each dielectric-isolated bulk finFET device including a fin that is isolated from a substrate by an oxide layer formed under an active portion of the fin,
wherein:
a second structure that includes the plurality of dielectric-isolated bulk finFET devices and the plurality of bulk finFET devices is formed by:
forming a second isolation layer over a first structure including a plurality of partially exposed fins and horizontal areas including a first isolation layer;
removing the second isolation layer from horizontal areas over the first isolation layer of the first portion of the first structure;
forming the oxide layer under active portions of the plurality of partially exposed fins of the first portion of the first structure; and
removing the second isolation layer in order to expose the plurality of partially exposed fins and horizontal areas of first structure to form the second structure.
2. The finFET circuit of claim 1 , wherein forming the second isolation layer comprises forming a silicon nitride layer, and wherein forming the second isolation layer is performed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD).
3. The finFET circuit of claim 1 , wherein the first structure comprises a plurality of fins formed on the substrate, wherein the plurality of fins are partially exposed above the first isolation layer, and wherein exposed portions of the plurality of fins are the active portions of the plurality of fins.
4. The finFET circuit of claim 3 , wherein the substrate comprises silicon, and wherein the first isolation layer comprises a shallow-trench isolation (STI) layer.
5. The finFET circuit of claim 1 , wherein the first portion of the first structure comprises a fin-on-oxide region, wherein the second isolation layer is removed from horizontal areas of the first portion of the first structure by forming a mask over a remaining portion of first structure using a spacer-etch process, and wherein the remaining portion of first structure comprises a bulk-fin region.
6. The finFET circuit of claim 1 , wherein the oxide layer under the fins of the first portion of the first structure is formed by an oxidation process, for which the first isolation layer is not a barrier.
7. The finFET circuit of claim 1 , further comprising gate regions formed over the plurality of partially exposed fins of the second structure.
8. The finFET circuit of claim 7 , wherein the gate regions comprise a gate oxide layer, a high-K dielectric layer, and a work-function metal and gate metal layer that is formed over the plurality of partially exposed fins of the second structure.
9. A communication device, comprising:
a fin field-effect transistor (finFET) integrated circuit that comprises a plurality of bulk finFET devices and a plurality of dielectric-isolated bulk finFET devices,
wherein:
each dielectric-isolated bulk finFET device includes a fin that is isolated from a substrate by an oxide layer formed under an active portion of the fin, and
a second structure that includes the plurality of dielectric-isolated bulk finFET devices and the plurality of bulk finFET devices is formed by:
forming a second isolation layer over a first structure including a plurality of partially exposed fins and horizontal areas including a first isolation layer;
removing the second isolation layer from horizontal areas over the first isolation layer of the first portion of the first structure;
forming the oxide layer under active portions of the plurality of partially exposed fins of the first portion of the first structure; and
removing the second isolation layer in order to expose the plurality of partially exposed fins and horizontal areas of first structure to form the second structure.
10. The communication device of claim 9 , wherein forming the second isolation layer comprises forming a silicon nitride layer, and wherein forming the second isolation layer is performed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD).
11. The communication device of claim 9 , wherein the first structure comprises a plurality of fins formed on the substrate, wherein the plurality of fins are partially exposed above the first isolation layer, and wherein exposed portions of the plurality of fins are the active portions of the plurality of fins.
12. The communication device of claim 9 , wherein the substrate comprises silicon, and wherein the first isolation layer comprises a shallow-trench isolation (STI) layer, and where the plurality of bulk finFET devices and the plurality of dielectric-isolated bulk finFET devices comprise gate regions formed over the plurality of partially exposed fins of the second structure.