Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding
View Patent ↗An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.
1. An apparatus comprising:
a control circuit configured to read data from and write data to a memory configured to store two or more bits per cell; and
an adaptive strength error correction code (ECC) decoder enabled to perform a plurality of different strength error correction code (ECC) decoding processes, wherein (i) after writing data to a least significant bit (LSB) page in the memory, the control circuit checks the data stored in the LSB page using a first strength error correction code (ECC) decoding process of the adaptive strength error correction code (ECC) decoder, and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page in the memory, the control circuit checks the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process of the adaptive strength error correction code (ECC) decoder.
2. The apparatus according to claim 1 , wherein the first strength is lower than the second strength.
3. The apparatus according to claim 1 , wherein writing data to the MSB page is separated in time from writing data to the LSB page.
4. The apparatus according to claim 1 , wherein the adaptive error correction code decoder is configured to switch between the first strength ECC decoding process and the second strength ECC decoding process.
5. The apparatus according to claim 1 , wherein the control circuit and the adaptive strength ECC decoder are part of a solid state disk (SSD) controller.
6. The apparatus according to claim 5 , wherein the controller is further configured to store metadata indicating a result of reading the LSB page with the first strength ECC decoding process.
7. The apparatus according to claim 6 , wherein the metadata is stored in at least one of the controller and a memory device connected to the controller.
8. The apparatus according to claim 6 , wherein the controller is configured to adjust a writing process for the MSB page based upon the stored metadata indicating a result of reading the LSB page with the first strength ECC decoding process.
9. The apparatus according to claim 6 , wherein the controller is configured to write data to the MSB page that can assist decoding the LSB page based upon the stored metadata.
10. The apparatus according to claim 6 , wherein the controller is configured to adjust a decoding process performed on the LSB and MSB pages based upon the stored metadata.
11. A method of writing data to a memory device configured to store two or more bits per cell, the method comprising;
writing data to a least significant bit (LSB) page in the memory device;
after writing data to the LSB page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process;
writing data to a most significant bit (MSB) page associated with the LSB page in the memory device; and
after writing data to the MSB page associated with the LSB page, checking the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.
12. The method according to claim 11 , wherein the LSB and MSB pages have a common wordline.
13. The method according to claim 11 , wherein the first strength is lower than the second strength.
14. The method according to claim 11 , wherein the step of writing data to the MSB page is separated in time from the step of writing data to the LSB page.
15. The method according to claim 11 , further comprising:
storing metadata indicating a result of reading the LSB page with the first strength ECC decoding process.
16. The method according to claim 15 , further comprising:
adjusting a writing process for the MSB page based upon the stored metadata indicating a result of reading the LSB page with the first strength ECC decoding process.
17. The method according to claim 15 , further comprising:
writing data to the MSB page that can assist decoding the LSB page based upon the stored metadata.
18. The method according to claim 15 , further comprising:
adjusting a decoding process performed on the LSB and MSB pages based upon the stored metadata.
19. An apparatus comprising:
a memory configured to store two or more bits per cell; and
a controller configured to write data in a two-step process, wherein (i) after writing data to a least significant bit (LSB) page in the memory, the controller checks the data stored in the LSB page using a first strength error correction code (ECC) decoding process, and (ii) after writing data to a most significant bit (MSB) page associated with the LSB page in the memory, the controller checks the data stored in both the LSB and MSB pages using a second strength error correction code (ECC) decoding process.
20. The apparatus according to claim 19 , wherein the memory and the controller are implemented as a solid state disk (SSD) drive.