Method of manufacturing semiconductor device and method of testing the same
View Patent ↗A method of manufacturing a semiconductor device according to the present invention includes, in a silicon substrate of the semiconductor chip, providing two TSVs (Through-Silicon-Vias) that are formed such that interfaces with the silicon substrate are covered with insulating films and bottom surface sides thereof do not penetrate through the silicon substrate, providing a high concentration impurity region in a peripheral region of the bottom surface sides of the TSVs in the silicon substrate, connecting a test circuit to the TSVs, inputting a test signal from one of the TSVs and detecting the test signal output via the high concentration impurity region and the other TSV, thereby evaluating a failure of the semiconductor chip, thinning a bottom surface of the semiconductor chip and removing the high concentration impurity region.
1. A method of manufacturing a semiconductor device comprising:
in a silicon substrate of a semiconductor chip,
providing two TSVs (Through-Silicon-Vias), the two TSVs being formed such that interfaces with the silicon substrate are covered with insulating films and bottom surface sides thereof do not penetrate through the silicon substrate;
providing a high concentration impurity region in a peripheral region of the bottom surface sides of the two TSVs in the silicon substrate, wherein the high concentration impurity region is buried inside the silicon substrate so that the high concentration impurity region does not reach any surface of the silicon substrate, wherein the high concentration impurity region is separated from the two TSVs by the insulating films;
connecting a test circuit to the two TSVs;
inputting a test signal from one of the two TSVs and detecting an output of the test signal via the high concentration impurity region and the other of the two TSVs, thereby evaluating a failure of the semiconductor chip;
thinning a bottom surface of the semiconductor chip and removing the high concentration impurity region; and
laminating the semiconductor chip after the thinning.
2. A method of testing a semiconductor device comprising:
in a silicon substrate of a semiconductor chip,
providing two TSVs (Through-Silicon-Vias), the two TSVs being formed such that interfaces with the silicon substrate are covered with insulating films and bottom surface sides thereof do not penetrate through the silicon substrate;
providing a high concentration impurity region in a peripheral region of the bottom surface sides of the two TSVs in the silicon substrate, wherein the high concentration impurity region is buried inside the silicon substrate so that the high concentration impurity region does not reach any surface of the silicon substrate, wherein the high concentration impurity region is separated from the two TSVs by the insulating films;
connecting a test circuit to the two TSVs; and
inputting a test signal from one of the two TSVs and detecting an output of the test signal via the high concentration impurity region and the other of the two TSVs, thereby evaluating a failure of the semiconductor chip.