Method and System for Optimizing Routing Layers and Board Space Requirements for a Ball Grid Array Land Pattern
A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid land pattern is described. A number of required pads is determined. A land pattern to yield the required pads is selected. A number of required perimeter routing channels is determined. A size of the land pattern to yield the required perimeter routing channels is optimized. At least one perimeter edge of the land pattern is under populated. In a further aspect, a number of layers is determined when a substrate has multiple layers.
1 . (canceled)
2 . An integrated circuit device comprising:
an integrated circuit mounted to a first side of a substrate; and
a plurality of conductive elements disposed on a second side of the substrate, at least a portion of the plurality of conductive elements being arranged in a grid pattern comprising rows and columns, including a grid perimeter,
wherein the grid perimeter includes a sequence of a first space, a first conductive element of the plurality of conductive elements, a second conductive element of the plurality of conductive elements, a second space, a third conductive element of the plurality of conductive elements, and a fourth conductive element of the plurality of conductive elements.
3 . The integrated circuit device of claim 2 , wherein the plurality of conductive elements are arranged to form a ball grid array.
4 . The integrated circuit device of claim 2 , wherein the rows of the grid pattern comprise a row immediately adjacent to the grid perimeter that is fully populated with conductive elements.
5 . The integrated circuit device of claim 2 , wherein the columns of the grid pattern comprise a column immediately adjacent to the grid perimeter that is fully populated with conductive elements.
6 . The integrated circuit device of claim 2 , wherein the sequence further comprises:
a third space immediately adjacent to the fourth conductive element.
7 . The integrated circuit device of claim 2 , wherein the sequence further comprises:
a fifth conductive element of the plurality of conductive elements immediately adjacent to the fourth conductive element.
8 . The integrated circuit device of claim 2 , wherein the number of conductive elements in a side of the grid perimeter is at least twice the number of spaces in the side of the grid perimeter.
9 . The integrated circuit device of claim 2 , wherein the first space replaces a conductive element in the grid pattern.
10 . A circuit board device comprising:
an integrated circuit mounted to a first side of a substrate; and
a circuit board mounted to a second side of the substrate through a plurality of conductive elements,
wherein at least a portion of the plurality of conductive elements is arranged in a grid pattern, the grid pattern having a perimeter that includes a sequence of a first space, a first conductive element of the plurality of conductive elements, a second conductive element of the plurality of conductive elements, a second space, a third conductive element of the plurality of conductive elements, and a fourth conductive element of the plurality of conductive elements.
11 . The circuit board device of claim 10 , further comprising:
at least one space, located inside of the perimeter, representing a position in the grid pattern that is not populated by a conductive element.
12 . The circuit board device of claim 10 , wherein the sequence further comprises:
a third space on the perimeter immediately adjacent to the fourth conductive element.
13 . The circuit board device of claim 10 , wherein the sequence further comprises:
a fifth conductive element of the plurality of conductive elements on the perimeter immediately adjacent to the fourth conductive element.
14 . The circuit board device of claim 10 , further comprising:
a routing channel passing through at least one of the first space and the second space.
15 . The circuit board device of claim 9 , wherein the number of conductive elements in a side of the perimeter is at least twice the number of spaces in the side of the perimeter.
16 . An integrated circuit device comprising:
an integrated circuit mounted to a first side of a substrate; and
a plurality of conductive elements disposed on a second side of the substrate, at least a portion of the plurality of conductive elements being arranged in a grid pattern, including a grid perimeter,
wherein a side of the grid perimeter includes a sequence of a first conductive element of the plurality of conductive elements, a first space, a second conductive element of the plurality of conductive elements, a third conductive element of the plurality of conductive elements, a second space, and a fourth conductive element of the plurality of conductive elements.
17 . The integrated circuit device of claim 16 , wherein the sequence further comprises:
a fifth conductive element of the plurality of conductive elements immediately adjacent to the fourth conductive element.
18 . The integrated circuit device of claim 16 , wherein the number of conductive elements included in the side of the grid perimeter is at least twice the number of spaces included in the side of the grid perimeter.
19 . The integrated circuit device of claim 16 , wherein the substrate comprises at least two layers.
20 . The integrated circuit device of claim 16 , wherein at least one position in the grid pattern, inside of the grid perimeter, is not occupied by a conductive element.
21 . The integrated circuit device of claim 16 , further comprising:
a routing channel passing, through the first space to a conductive element in the grid pattern located inside of the grid perimeter.