Multilevel hybrid inverter and operating method
An inverter comprises a first boost apparatus, a second boost apparatus, a first half-cycle switching network coupled to the first boost apparatus, wherein the first half-cycle switching network is configured such that a first three-level conductive path is formed when a voltage at a dc source is greater than an instantaneous value of a voltage at an output of the inverter and a first five-level conductive path is formed when the instantaneous value of the voltage at the output of inverter is greater than the voltage at the dc source.
1. A method comprising:
detecting a voltage across a dc source coupled to an inverter, wherein the inverter comprises:
a first boost apparatus having an input coupled to a first terminal of the dc source;
a second boost apparatus having an input coupled to a second terminal of the dc source; and
a converting stage coupled to an output filter comprising a first half-cycle switching network and a second half-cycle switching network, wherein:
the first half-cycle switching network comprises a first three-level conductive path and a first five-level conductive path; and
the second half-cycle switching network comprises a second three-level conductive path and a second five-level conductive path;
in a first half-cycle of a voltage at an output of the output filter, enabling the first three-level conductive path when a voltage at the first terminal of the dc source is greater than an instantaneous value of the voltage at the output of the output filter;
in the first half-cycle, enabling the first five-level conductive path when the instantaneous value of the voltage at the output of the output filter is greater than the voltage at the first terminal of the dc source;
in a second half-cycle of the voltage at the output of the output filter, enabling the second three-level conductive path when the instantaneous value of the voltage at the output of the output filter is greater than the voltage at the second terminal of the dc source; and
in the second half-cycle, enabling the second five-level conductive path when the voltage at the second terminal of the dc source is greater than the instantaneous value of the voltage at the output of the output filter.
2. The method of claim 1 , wherein:
the first three-level conductive path is formed by Q 5 coupled between the input of the output filter and the first terminal of the dc source, and Q 3 and Q 7 connected in series and coupled between the input of the output filter and the first terminal of the dc source;
the first five-level conductive path is formed by Q 5 coupled between the input of the output filter and the first terminal of the dc source, Q 1 and Q 5 connected in series and coupled between an output of the first boost apparatus and the input of the output filter, and Q 7 and Q 11 connected in series and coupled between the output of the first boost apparatus and the input of the output filter;
the second three-level conductive path is formed by Q 6 coupled between the input of the output filter and the second terminal of the dc source, and Q 4 and Q 8 connected in series and coupled between the input of the output filter and the second terminal of the dc source; and
the second five-level conductive path is formed by Q 6 coupled between the input of the output filter and the second terminal of the dc source, Q 2 and Q 6 connected in series and coupled between an output of the second boost apparatus and the input of the output filter, and Q 8 and Q 12 connected in series and coupled between the output of the second boost apparatus and the input of the output filter.
3. The method of claim 2 , further comprising:
turning on Q 3 before turning on Q 5 ;
turning off Q 5 before turning off Q 3 ;
turning on Q 4 before turning on Q 6 ; and
turning off Q 6 before turning off Q 4 .
4. The method of claim 2 , further comprising:
turning on Q 3 before turning on Q 5 ;
turning off Q 3 after Q 5 is turned on;
turning on Q 3 before turning off Q 5 ;
turning off Q 5 after Q 3 is turned on; and
turning off Q 3 .
5. The method of claim 2 , further comprising:
turning on Q 4 before turning on Q 6 ;
turning off Q 4 after Q 6 is turned on;
turning on Q 4 before turning off Q 6 ;
turning off Q 6 after Q 4 is turned on; and
turning off Q 4 .
6. The method of claim 2 , further comprising:
turning on Q 11 before turning on Q 1 ;
turning off Q 1 before turning off Q 11 ;
turning on Q 12 before turning on Q 2 ; and
turning off Q 2 before turning off Q 12 .
7. The method of claim 2 , further comprising:
turning on RL 1 and RL 2 so as to bypass a first diode and a second diode when a voltage across the dc source is greater than a peak-to-peak value of the voltage at the output of the output filter, wherein:
the first diode is coupled between the first terminal of the dc source and a common node of Q 1 and Q 5 ; and
the second diode is coupled between the second terminal of the dc source and a common node of Q 2 and Q 6 .
8. A method comprising:
providing an inverter coupled to a dc source, wherein the inverter comprises:
a first boost apparatus having an input coupled to a first terminal of the dc source;
a second boost apparatus having an input coupled to a second terminal of the dc source;
a first half-cycle switching network coupled to an output filter comprising:
a first three-level conductive path coupled to the first terminal of the dc source; and
a first five-level conductive path coupled to the first terminal of the dc source and an output of the first boost apparatus; and
a second half-cycle switching network coupled to the output filter comprising:
a second three-level conductive path coupled to the second terminal of the dc source; and
a second five-level conductive path coupled to the second terminal of the dc source and an output of the second boost apparatus;
a first diode is coupled between the first terminal of the dc source and the first half-cycle switching network; and
a second diode is coupled between the second terminal of the dc source and the second half-cycle switching network; and
bypassing the first diode and the second diode when a voltage across the dc source is greater than a peak-to-peak value of a voltage at an output of the output filter.
9. The method of claim 8 , further comprising:
in a first half-cycle of a voltage at an output of the output filter, enabling the first three-level conductive path when a voltage at the first terminal of the dc source is greater than an instantaneous value of the voltage at the output of the output filter.
10. The method of claim 9 , further comprising:
in the first half-cycle, enabling the first five-level conductive path when the instantaneous value of the voltage at the output of the output filter is greater than the voltage at the first terminal of the dc source.
11. The method of claim 8 , further comprising:
in a second half-cycle of the voltage at the output of the output filter, enabling the second three-level conductive path when an instantaneous value of the voltage at the output of the output filter is greater than the voltage at the second terminal of the dc source.
12. The method of claim 11 , wherein:
in the second half-cycle, enabling the second five-level conductive path when the voltage at the second terminal of the dc source is greater than the instantaneous value of the voltage at the output of the output filter.
13. The method of claim 8 , wherein:
the inverter is a five-level inverter.
14. The method of claim 13 , wherein:
a first level of the inverter is coupled to the output of the second boost apparatus;
a second level of the inverter is coupled to the second terminal of the dc source;
a third level of the inverter is coupled to ground;
a fourth level of the inverter is coupled to the second terminal of the dc source; and
a fifth level of the inverter is coupled to the output of the second boost apparatus.
15. A device comprising:
a first boost apparatus having an input coupled to a first terminal of a dc source;
a second boost apparatus having an input coupled to a second terminal of the dc source;
a first half-cycle switching network, wherein:
the first half-cycle switching network is coupled to an input of an output filter and the first boost apparatus; and
the first half-cycle switching network is coupled to the input of the output filter and the first terminal of the dc source through a first diode, and wherein the half-cycle switching network is configured such that:
a first three-level conductive path is coupled between the first terminal of the dc source and the input of the output filter when a voltage at the first terminal of the dc source is greater than an instantaneous value of a voltage at an output of the output filter; and
a first five-level conductive path is coupled to the first terminal of the dc source and an output of the first boost apparatus when the instantaneous value of the voltage at the output of the output filter is greater than the voltage at the first terminal of the dc source;
a second half-cycle switching network, wherein:
the second half-cycle switching network is coupled to the input of the output filter and the second boost apparatus; and
the second half-cycle switching network is coupled to the input of the output filter and the second terminal of the dc source through a second diode.
16. The device of claim 15 , wherein the second half-cycle switching network is configured such that:
a second three-level conductive path is coupled between the second terminal of the dc source and the input of the output filter when the instantaneous value of the voltage at the output of the output filter is greater than a voltage at the second terminal of the dc source; and
a second five-level conductive path is coupled to the second terminal of the dc source and an output of the second boost apparatus when the voltage at the second terminal of the dc source is greater than the instantaneous value of the voltage at the output of the output filter.
17. The device of claim 16 , wherein:
the first three-level conductive path is formed by Q 5 coupled between the input of the output filter and the first terminal of the dc source, and Q 3 and Q 7 connected in series and coupled between the input of the output filter and the first terminal of the dc source;
the first five-level conductive path is formed by Q 5 coupled between the input of the output filter and the first terminal of the dc source, Q 1 and Q 5 connected in series and coupled between an output of the first boost apparatus and the input of the output filter, and Q 7 and Q 11 connected in series and coupled between the output of the first boost apparatus and the input of the output filter;
the second three-level conductive path is formed by Q 6 coupled between the input of the output filter and the second terminal of the dc source, and Q 4 and Q 8 connected in series and coupled between the input of the output filter and the second terminal of the dc source; and
the second five-level conductive path is formed by Q 6 coupled between the input of the output filter and the second terminal of the dc source, Q 2 and Q 6 connected in series and coupled between an output of the second boost apparatus and the input of the output filter, and Q 8 and Q 12 connected in series and coupled between the output of the second boost apparatus and the input of the output filter.
18. The device of claim 15 , further comprising:
a first relay connected in parallel with the first diode; and
a second relay connected in parallel with the second diode.
19. The device of claim 18 , wherein:
the first diode and the second diode are configured to be bypassed by turning on the first relay and the second relay when a voltage across the dc source is greater than a peak-to-peak value of the voltage at the output of the output filter.
20. The device of claim 15 , wherein:
the first boost apparatus comprises a first input inductor, a first low side switch and a first blocking diode; and
the second boost apparatus comprises a second input inductor, a second low side switch and a second blocking diode.