Memory access bases on erase cycle time
View Patent ↗Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality of indicators for the memory block. The indicator is saved and later retrieved during a read operation.
1. A method, comprising:
measuring an erase-time of a memory block in a memory device;
comparing the erase-time with a threshold value;
storing at least one indicator for the memory block, a value of the at least one indicator being based on the comparing;
selecting a reference cell from a plurality of reference cells based on the value of the indicator; and
reading data from the memory block with the selected reference cell.
2. The method of claim 1 , wherein the at least one indicator is set to a first value when the erase-time of the memory block exceeds the threshold value, and is set to a second value when the erase-time of the memory block is less than the threshold value.
3. The method of claim 1 , wherein a plurality of indicators are set based on a plurality of threshold values.
4. The method of claim 1 , wherein the storing comprises storing the at least one indicator in a non-volatile memory.
5. The method of claim 4 , further comprising loading the at least one indicator from the non-volatile memory to a latch during a Power-On-Reset (POR).
6. The method of claim 1 , further comprising storing the at least one indicator in a latch.
7. A method, comprising:
receiving a command to read data from a memory block;
accessing an indicator associated with the memory block, wherein the indicator is stored in a status cell within a volatile memory, the status cell being associated with the memory block;
selecting a reference cell from a plurality of reference cells based on a value of the indicator; and
reading the data with the selected reference cell.
8. The method of claim 7 , wherein the selecting comprises:
selecting a first reference cell if the indicator is a first value, and selecting a second reference cell if the indicator is a second value.
9. The method of claim 8 , wherein the indicator has a first value if an erase-time of the memory block was previously determined to be less than a threshold, and wherein the indicator has a second value if the erase-time of the memory block was previously determined to be greater than the threshold.
10. The method of claim 7 , wherein each of the plurality of reference cells is associated with a different current value.
11. The method of claim 7 , further comprising loading the indicator from a non-volatile memory to a latch during a POR.
12. A memory device, comprising:
measuring circuitry configured to measure an erase-time of a memory block in a memory device;
a processing module configured to compare the erase-time with a threshold value; and
a controller module configured to:
store an indicator for the memory block, a value of the indicator being based on the comparing, and
select a reference cell from a plurality of reference cells based on the value of the indicator; and
read data from the memory block with the selected reference cell.
13. The memory device of claim 12 , wherein the indicator is set to a first value when the erase-time of the memory block exceeds the threshold value, and is set to a second value when the erase-time of the memory block is less than the threshold value.
14. The memory device of claim 12 , wherein the indicator is set based on a plurality of threshold values.
15. The memory device of claim 12 , wherein the controller module is configured to store the indicator in a non-volatile memory.
16. The memory device of claim 15 , wherein the controller module is further configured to load the indicator from the non-volatile memory to a latch during a POR.
17. The memory device of claim 12 , wherein the controller module is configured to store the indicator in a latch.
18. The memory device of claim 17 , wherein the controller module is further configured to map the indicator saved in the latch to a reference cell different from an original reference cell.
19. The method of claim 1 , wherein each of the plurality of reference cells is associated with a different current value.
20. The memory device of claim 12 , wherein each of the plurality of reference cells is associated with a different current value.