Method of integrating a charge-trapping gate stack into a CMOS flow

1. A method comprising:

forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric;

forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer;

patterning the cap layer and the dielectric stack to form a gate stack of a memory device;

removing the second cap layer; and

performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer.

2. The method of claim 1 , wherein the first cap layer and the second cap layer comprise a material comprising nitride.

3. The method of claim 1 , wherein the oxidation process consumes a portion of the charge-trapping layer.

4. The method of claim 1 , wherein the oxidation process does not consume substantially any of the charge-trapping layer.

5. The method of claim 1 , wherein the charge-trapping layer comprises a multi-layer charge-trapping layer including at least a first charge-trapping layer closer to the tunneling dielectric, and an second charge-trapping layer that is oxygen-lean relative to the first charge-trapping layer and comprises a majority of a charge traps distributed in multi-layer charge-trapping layer.

6. The method of claim 5 , wherein the second charge-trapping layer and the cap layer comprise the same material.

7. The method of claim 1 , wherein the first cap layer and the second cap layer comprise silicon nitride or silicon oxynitride.

8. A method comprising:

forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer on the tunneling dielectric;

forming a cap layer on the charge-trapping layer;

patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and

removing at least a portion of the cap layer in the first region of the substrate;

performing an oxidation process to form a gate oxide overlying the surface of the substrate in the second region while concurrently oxidizing a remaining portion of the cap layer to form a blocking oxide on the charge-trapping layer.

9. The method of claim 8 , wherein the oxidation process consumes substantially all of the remaining portion of the cap layer.

10. The method of claim 8 , wherein the oxidation process consumes a portion of the charge-trapping layer.

11. The method of claim 8 , wherein the charge-trapping layer comprises a multi-layer charge-trapping layer including at least a first charge-trapping layer closer to the tunneling dielectric, and an second charge-trapping layer that is oxygen-lean relative to the first charge-trapping layer and comprises a majority of a charge traps distributed in multi-layer charge-trapping layer.

12. The method of claim 11 , wherein the second charge-trapping layer and the cap layer comprise the same material.

13. The method of claim 8 , wherein the cap layer comprises silicon nitride or silicon oxynitride.

14. A method comprising:

forming a dielectric stack in a first region and over a pad oxide in a second region of a substrate, the dielectric stack including a tunneling dielectric overlying a surface of the substrate and a charge-trapping layer on the tunneling dielectric;

forming a cap layer overlying the dielectric stack;

forming a sacrificial oxide over the cap layer;

patterning the sacrificial oxide, cap layer and dielectric stack to form a gate stack in the first region of the substrate, and to remove the sacrificial oxide, cap layer and dielectric stack from the second region of the substrate;

removing the sacrificial oxide from the gate stack while removing the pad oxide from the second region; and

forming a gate oxide overlying the surface of the substrate in the second region using an oxidation process while concurrently oxidizing at least a portion of the cap layer to form a blocking oxide overlying the charge-trapping layer.

15. The method of claim 14 , wherein the oxidation process consumes substantially all of the cap layer.

16. The method of claim 15 , wherein the oxidation process consumes a portion of the charge-trapping layer.

17. The method of claim 15 , wherein the oxidation process does not consume substantially any of the charge-trapping layer.

18. The method of claim 14 , wherein the charge-trapping layer comprises a multi-layer charge-trapping layer including at least a first charge-trapping layer closer to the tunneling dielectric, and an second charge-trapping layer that is oxygen-lean relative to the first charge-trapping layer and comprises a majority of a charge traps distributed in multi-layer charge-trapping layer.

19. The method of claim 18 , wherein the second charge-trapping layer and the cap layer comprise the same material.

20. The method of claim 14 , wherein the first cap layer and the second cap layer comprise silicon nitride or silicon oxynitride.