Granted Patent B2

US 9,607,568 · App. 14/201,591 · Granted Mar 28, 2017

Abstract

Claims (97)

1. A display panel driver, comprising:

a grayscale amplifier receiving an input grayscale reference voltage and generating an output grayscale reference voltage corresponding to said input grayscale reference voltage;

a voltage dividing resistor receiving said output grayscale reference voltage and generating a plurality of grayscale voltages by using said received output grayscale reference voltage;

a decoder circuit selecting grayscale voltages from among said plurality of grayscale voltages in response to image data and outputting said selected grayscale voltages; and

an output circuit outputting drive voltages corresponding to said selected grayscale voltages to output terminals to be connected to source lines of a display panel,

wherein said grayscale amplifier is configured such that said output grayscale reference voltage is adjustable by adjusting an offset voltage of said grayscale amplifier,

wherein said grayscale amplifier includes:

an input node receiving said input grayscale reference voltage;

an input stage;

an output stage; and

an output node outputting said output grayscale reference voltage,

wherein said input stage comprises:

a first MOS transistor having a source connected to a first node, a gate connected to said input node and a drain connected to a second node;

a second MOS transistor having a source connected to said first node, a gate connected to said output node and a drain connected to a third node; and

first and second output voltage adjustment circuits,

wherein said output stage is configured to output said output grayscale reference voltage from said output node in response to a first current flowing through said second node and a second current flowing through said third node,

wherein said first output voltage adjustment circuit includes at least one adjustment leg connected between said first and second nodes,

wherein said first adjustment leg comprises:

a first switch; and

a third MOS transistor having a gate connected to said input node,

wherein said first switch and said third MOS transistor are connected in series between said first and second nodes,

wherein said second output voltage adjustment circuit includes at least one second adjustment leg connected between said first and third nodes,

wherein said second adjustment leg comprises:

a second switch and

a fourth MOS transistor having a gate connected to said output node,

wherein said second switch and said fourth MOS transistor are connected in series between said first and third node, and

wherein said first and second switches are controlled in response to said control signal.

2. The display panel driver according to claim 1 , wherein the offset voltage of said grayscale amplifier is controlled in response to a control signal generated in response to adjustment data stored in a non-volatile manner.

3. The display panel driver according to claim 2 , further comprising:

a storage section storing the adjustment data in the non-volatile manner,

wherein said storage section, said grayscale amplifier, said voltage dividing resistor, said decoder circuit and said output circuit are monolithically integrated.

4. The display panel driver according to claim 1 , wherein said input stage further comprises a constant current source which draws or supplies a constant current from or to said first node.

5. A display device, comprising:

a display panel; and

a plurality of display panel drivers,

wherein each of said plurality of display panel drivers includes:

a grayscale amplifier receiving an input grayscale reference voltage and generating an output grayscale reference voltage corresponding to said input grayscale reference voltage;

a voltage dividing resistor receiving said output grayscale reference voltage and generating a plurality of grayscale voltages by using said received output grayscale reference voltage;

a decoder circuit selecting grayscale voltages from among said plurality of grayscale voltages in response to image data and outputting said selected grayscale voltages; and

an output circuit outputting drive voltages corresponding to said selected grayscale voltages to output terminals to be connected to source lines of said display panel,

wherein said grayscale amplifier is configured such that said output grayscale reference voltage is adjustable by adjusting an offset voltage of said grayscale amplifier,

wherein said grayscale amplifier includes:

an input node receiving said input grayscale reference voltage;

an input stage;

an output stage; and

an output node outputting said output grayscale reference voltage,

wherein said input stage comprises:

a first MOS transistor having a source connected to a first node, a gate connected to said input node and a drain connected to a second node;

a second MOS transistor having a source connected to said first node, a gate connected to said output node and a drain connected to a third node; and

first and second output voltage adjustment circuits,

wherein said output stage is configured to output said output grayscale reference voltage from said output node in response to a first current flowing through said second node and a second current flowing through said third node,

wherein said first output voltage adjustment circuit includes at least one adjustment leg connected between said first and second nodes,

wherein said first adjustment leg comprises:

a first switch; and

a third MOS transistor having a gate connected to said input node,

wherein said first switch and said third MOS transistor are connected in series between said first and second nodes,

wherein said second output voltage adjustment circuit includes at least one second adjustment leg connected between said first and third nodes,

wherein said second adjustment leg comprises:

a second switch and

a fourth MOS transistor having a gate connected to said output node,

wherein said second switch and said fourth MOS transistor are connected in series between said first and third node, and

wherein said first and second switches are controlled in response to said control signal.

6. The display device according to claim 5 , wherein the offset voltage of said grayscale amplifier is controlled in response to a control signal generated in response to adjustment data stored in a non-volatile manner.

7. A display device, comprising:

a display panel; and

a plurality of display panel drivers,

wherein each of said plurality of display panel drivers comprises:

a grayscale amplifier receiving an input grayscale reference voltage and generating an output grayscale reference voltage corresponding to said input grayscale reference voltage, said grayscale amplifier comprising a plurality of controllable devices, each responsive to an offset voltage adjustment signal, that adjust an offset voltage of said grayscale amplifier;

a voltage dividing resistor receiving said output grayscale reference voltage and generating a plurality of grayscale voltages by using said received output grayscale reference voltage;

a decoder circuit selecting grayscale voltages from among said plurality of grayscale voltages in response to image data and outputting said selected grayscale voltages; and

an output circuit outputting drive voltages corresponding to said selected grayscale voltages to output terminals to be connected to source lines of said display panel,

wherein said grayscale amplifier includes:

an input node receiving said input grayscale reference voltage;

an input stage;

an output stage; and

an output node outputting said output grayscale reference voltage,

wherein said input stage comprises:

a first MOS transistor having a source connected to a first node, a gate connected to said input node and a drain connected to a second node;

a second MOS transistor having a source connected to said first node, a gate connected to said output node and a drain connected to a third node; and

first and second output voltage adjustment circuits,

wherein said output stage is configured to output said output grayscale reference voltage from said output node in response to a first current flowing through said second node and a second current flowing through said third node,

wherein said first output voltage adjustment circuit includes at least one adjustment leg connected between said first and second nodes,

wherein said first adjustment leg comprises:

a first switch; and

a third MOS transistor having a gate connected to said input node,

wherein said first switch and said third MOS transistor are connected in series between said first and second nodes,

wherein said second output voltage adjustment circuit includes at least one second adjustment leg connected between said first and third nodes,

wherein said second adjustment leg comprises:

a second switch and

a fourth MOS transistor having a gate connected to said output node,

wherein said second switch and said fourth MOS transistor are connected in series between said first and third node, and

wherein said first and second switches are controlled in response to said control signal.

8. The display device according to claim 7 , further comprising a non-volatile memory device to store adjustment data providing offset voltage adjustment data for offset voltage adjustment signals to adjust said offset voltage.

9. The display device according to claim 8 , wherein said non-volatile memory device comprises a memory device component within each said display panel driver.

10. The display device according to claim 8 , wherein said non-volatile memory device comprises a memory device used to control each grayscale amplifier of a plurality of grayscale amplifiers.

11. The display device according to claim 7 , wherein said plurality of controllable devices comprises a plurality of switches, each respectively responsive to an offset voltage adjustment signal.

12. The display device according to claim 11 , wherein said grayscale amplifier comprises a plurality of transistors interconnected in a parallel configuration, each said transistor respectively switched by a switch serially-connected with the transistor, said serially-connected switch comprising one controllable device of said plurality of controllable devices, each of the serially-connected switches being responsive to an offset voltage adjustment signal.

Assignments (6)