Systems and methods for optimizing data storage among a plurality of solid state memory subsystems
A solid state storage device includes an interface system configured to communicate with an external host system over an aggregated multi-channel interface to receive data for storage by the solid state storage device. The solid state storage device also includes a storage processing system configured to communicate with the interface system to receive the data, process the data against storage allocation information to parallelize the data among a plurality of solid state memory subsystems, and transfer the parallelized data. The interface system is configured to receive the parallelized data, apportion the parallelized data among the plurality of solid state memory subsystems, and transfer the parallelized data for storage in the plurality of solid state memory subsystems, where each of the plurality of solid state memory subsystems is configured to receive the associated portion of the parallelized data and store the associated portion on a solid state storage medium.
1. A method of operating a data storage device, the method comprising:
monitoring a utilization level of at least a processing system of the data storage device;
determining a quantity of links to aggregate for an external communication interface of the data storage device based at least on the utilization level of at least the processing system;
providing an indication of the quantity of links to aggregate for the external communication interface to an interface system of the data storage device;
providing an indication of the utilization level to a control circuit of the data storage device; and
throttling a clock frequency associated with at least the processing system of the data storage device based at least on the indication of the utilization level.
2. The method of claim 1 , wherein throttling the clock frequency associated with at least the processing system of the data storage device based at least on the indication of the utilization level comprises changing the clock frequency proportional to the utilization level.
3. The method of claim 1 , further comprising:
determining a voltage level based at least on the indication of the utilization level;
providing a voltage signal at the voltage level to the processing system; and
wherein throttling the clock frequency comprises throttling the clock frequency based at least on the voltage signal.
4. The method of claim 1 , wherein monitoring the utilization level of at least the processing system of the data storage device comprises, in the processing system, executing a software process configured to monitor the utilization level of at least the processing system.
5. The method of claim 4 , further comprising:
in the processing system, providing the indication of the utilization level to an external pin of the processing system.
6. A data storage device, comprising:
a processing system configured to monitor a utilization level of at least the processing system;
the processing system configured to determine a quantity of links to aggregate for an external communication interface of the data storage device based at least on the utilization level of at least the processing system;
the processing system configured to provide an indication of the quantity of links to aggregate for the external communication interface to an interface system of the data storage device;
the processing system configured to provide an indication of the utilization level to a control circuit of the data storage device; and
the control circuit configured to throttle a clock frequency associated with at least the processing system based at least on the indication of the utilization level.
7. The data storage device of claim 6 , comprising:
the control circuit configured to change the clock frequency proportional to the utilization level to throttle the clock frequency.
8. The data storage device of claim 6 , comprising:
the control circuit configured to determine a voltage level based at least on the indication of the utilization level;
the control circuit configured to provide a voltage signal at the voltage level to the processing system; and
the processing system configured to throttle the clock frequency based at least on the voltage signal.
9. The data storage device of claim 6 , comprising:
the processing system configured to execute a software process configured to monitor the utilization level of at least the processing system.
10. The data storage device of claim 6 , comprising:
the processing system configured to provide the indication of the utilization level to an external pin of the processing system.