Tamper detection arrangement for integrated circuits

1. A tamper detection arrangement for use within an integrated circuit comprising:

a metal stack of interconnect metal layers;

at least one input capacitor having a first capacitance value; wherein the at least one capacitor is formed in the metal stack;

a feedback capacitor having a second capacitance value;

a sensing arrangement comprising an amplifier circuit having the at least one input capacitor as an input and the at least one feedback capacitor in a feedback loop across the amplifier circuit operable to detect a change in a ratio of capacitance values between the first capacitance value of the at least one input capacitor and the second capacitance value of the feedback capacitor; and

a protective shield to protect a sensitive area of the integrated circuit from tampering, the protective shield being provided by the at least one input capacitor.

2. The arrangement of claim 1 , wherein the amplifier circuit comprises a differential amplifier.

3. The arrangement of claim 1 , wherein gain of the amplifier circuit is dictated by the ratio of capacitance values between the first capacitance value of the at least one input capacitor and the second capacitance value of the feedback capacitor.

4. The arrangement of claim 1 , wherein the sensing arrangement is operable to detect a change in the ratio of the capacitance values when the structure of one of the capacitors is physically tampered with and to provide an output signal to indicate that physical tampering has occurred.

5. The arrangement of claim 1 , wherein at least a part of the at least one input capacitor is formed from at least one layer of the metal stack of the integrated circuit.

6. The arrangement of claim 1 , wherein the sensing arrangement comprises an amplifier and a plurality of switches, the amplifier and the plurality of switches being connected with the first and second capacitors to form a switched capacitor amplifier circuit.

7. The arrangement of claim 1 , wherein the switched capacitor amplifier circuit is a single ended switched capacitor amplifier circuit.

8. The arrangement of claim 1 , wherein the switched capacitor amplifier circuit is a differential switched capacitor amplifier circuit.

9. The arrangement of claim 1 , wherein the at least one feedback capacitor is positioned within the area overlaid by the protective shield.

10. The arrangement of claim 1 , wherein the area defined by the sensitive area is smaller than the area of the protective shield and within a plan boundary of the protective shield.

11. The arrangement of claim 1 , wherein a non-overlapping clock generator is a component of the sensing arrangement and is a component of the integrated circuit, the non-overlapping clock generator being positioned under the protective shield.

12. The arrangement of claim 1 , wherein one or more further input capacitors are superimposed over the at least one input capacitor to augment the protective shield.

13. The arrangement of claim 3 , wherein the feedback capacitor comprises one or more capacitors.

14. The arrangement of claim 1 , wherein plural ones of the at least one input capacitor are connected to the sensing arrangement by a multiplexer.

15. The apparatus of claim 14 , wherein sequencing of the multiplexer is changeable and/or is pseudo-random.

16. The arrangement of claim 14 , wherein the multiplexer switches such that different pairs of capacitors from the at least one input capacitor array are compared in respective measurement cycles.

17. The arrangement of claim 14 , wherein the plural ones of the at least one input capacitor are connected by the multiplexer to a single amplifier.

18. The arrangement of claim 1 , herein one or more of the at least one input capacitors are fringe capacitors.

19. The arrangement of claim 18 , wherein the feedback capacitor is not a fringe capacitor.

20. The arrangement of claim 18 , wherein at least some of the fringe capacitors comprise a plurality of interdigitated elongate fingers which are spaced apart from one another.

21. The arrangement of any one of claim 20 , wherein the fringe capacitors comprise at least first and second fringe capacitors, wherein finger patterns defined by the interdigitated fingers of the first and second fringe capacitors are the same as one another and are orientated differently from one another.

22. The arrangement of claim 1 , wherein one or more components of the sensing arrangement are components of the integrated circuit.

23. The arrangement of claim 22 , wherein all components of the sensing arrangement are components of the integrated circuit.

24. The arrangement of claim 23 , wherein all components of the tamper detection arrangement are components of the integrated circuit.

25. An integrated circuit incorporating the tamper detection arrangement of claim 1 .

26. An integrated circuit package incorporating the integrated circuit of claim 25 .

27. A method of detecting physical tampering with an integrated circuit, the method comprising:

providing a metal stack of interconnect metal layers;

providing at least one input capacitor having a first capacitance value; wherein the at least one capacitor is formed in the metal stack; .

providing a feedback capacitor having a second capacitance value;

providing a sensing arrangement operable to detect tampering using an amplifier circuit having the at least one input capacitor as an input and the at least one feedback capacitor in a. feedback loop across the amplifier operable to detect a change in a ratio of capacitance values between the first capacitance value of the at least one input capacitor and the second capacitance value of the feedback capacitor;

forming a protective shield to protect a sensitive area of the integrated circuit from at least a part of the at least one input capacitor.

28. The method of claim 27 , further comprising providing an output signal that indicates that physical tampering with of the integrated circuit has occurred.