Delay-locked loop (DLL) operation mode controller circuit and method for controlling thereof
View Patent ↗A delay-locked loop (DLL) operation mode control circuit and corresponding method are provided in which one of the output values from a display driver IC (DDI) is detected to switch a DLL block to standby mode. In examples, a CLKP/N frequency and CLKP/N common terminal voltage status are used to switch mode. Accordingly, since inoperable frequency domains otherwise present in a normal mode interval of the DLL block is included into standby mode, more stable operation of the DLL circuit is provided.
1. A delay-locked loop (DLL) operation mode control circuit, comprising:
a first comparing unit configured to compare a clock frequency of a display driver IC (DDI) with a reference frequency;
a second comparing unit configured to compare a common terminal voltage of the DDI with a reference voltage; and
a logic gate configured to output a standby enable signal used to switch a DLL circuit to standby mode, in response to a standby mode switch signal being applied from at least one of the first and second comparing units.
2. The DLL operation mode control circuit of claim 1 , wherein the DLL circuit comprises a comparing unit, a phase frequency detector, a charge pump, and a voltage control delay line (VCDL).
3. The DLL operation mode control circuit of claim 2 , wherein the standby mode switch signal is applied to each one of the comparing unit, a phase frequency detector, a charge pump, and the voltage control delay line.
4. The DLL operation mode control circuit of claim 2 , wherein the DLL circuit is configured to receive clock frequency CLKP and CLKN signals of the DDI at the comparing unit.
5. The DLL operation mode control circuit of claim 1 , wherein the first comparing unit comprises:
a first comparator configured to receive clock frequency CLKP and CLKN signals of the DDI;
a low-pass filter configured to filter an original output frequency from the first comparator; and
a controller configured to receive the original output frequency and an output frequency passed through the low-pass filter, and compare the number of rising edges of the original output frequency and the output frequency passed through the low-pass filter to generate the standby mode switch signal.
6. The DLL operation mode control circuit of claim 5 , wherein the output frequency from the first comparator represents a relationship between CLKP and CLKN.
7. The DLL operation mode control circuit of claim 5 , wherein the standby mode switch signal is generated when the numbers of rising edges of the output frequencies are equal.
8. The DLL operation mode control circuit of claim 5 , wherein the low-pass filter is configured to be associated with a frequency that is greater than or equal to a minimum normally operable frequency of the DLL circuit.
9. The DLL operation mode control circuit of claim 1 , wherein the first comparing unit generates the standby mode switch signal, in response to the clock frequency of the DDI being smaller than a normal operation frequency of the DLL circuit.
10. The DLL operation mode control circuit of claim 1 , wherein the logic gate is an OR gate.
11. The DLL operation mode control circuit of claim 10 , wherein one terminal of the OR gate is connected to the first comparing unit and another terminal of the OR gate is connected to the second comparing unit.
12. The DLL operation mode control circuit of claim 1 , wherein the second comparing unit generates the standby mode switch signal, in response to the common terminal voltage being greater than the reference voltage.
13. The DLL operation mode control circuit of claim 1 , wherein the second comparing unit comprises a second comparator comprising a non-inverting terminal (+) connected to a pull-up resistor and an internal voltage terminal to receive a common terminal voltage of clock frequency signals CLKP and CLKN, and an inverting terminal (−) to receive a preset reference voltage, and
the second comparator generates the standby mode switch signal, in response to the common terminal voltage being greater than the reference voltage.
14. A delay-locked loop (DLL) operation mode control method, comprising:
detecting, at a DLL operation mode control circuit, an operational status or a clock frequency of a display driver IC (DDI);
generating a standby mode switch signal in response to the operational status indicating abnormal operation or in response to the clock frequency being smaller than a preset DLL normal operation frequency; and
placing a DLL circuit into standby according to the standby mode switch signal.
15. The DLL operation mode control method of claim 14 , wherein the standby mode switch signal is generated according to the operational status, when clock frequency signals CLKP and CLKN of the DDI have high impedance (Hi-z) state.
16. The DLL operation mode control method of claim 14 , wherein the standby mode switch signal is generated as a first signal by a frequency comparing unit or as a second signal by a level comparing unit based on at least one of the operational status and the clock frequency.