IP Library Granted Patent US 9,218,816
Granted Patent B2
US 9,218,816 · App. 14/209,196 · Granted Dec 22, 2015

DAC device and audio system

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Quick Facts
Patent No.
US 9,218,816
App. No.
14/209,196
Granted
Dec 22, 2015
Kind
B2
Abstract

In a DAC device, a distortion correction function g1(x) of a harmonic obtained from a result of a frequency analysis on an analog output signal of a DAC circuit is obtained. A correction value is determined based on the correction function g1(x) in accordance with an input digital signal, and is previously stored in a memory. A nonlinear correction circuit reads a corresponding correction value from the memory in accordance with the value of a digital signal output from a digital filter, and transmits the correction value to a subtractor. The subtractor subtracts the correction value from the digital signal output from the digital filter.

Claims (47)

1. A digital-to-analog conversion (DAC) device comprising:

a subtraction section configured to subtract a correction value from an input digital signal;

a DAC circuit configured to receive the digital signal from which the correction value has been subtracted by the subtraction section, and to convert the digital signal to an analog signal; and

a correction value output section configured to output the correction value to the subtraction section, wherein:

the correction value is determined by using a distortion correction function,

the distortion correction function is predetermined based on a distortion component included in a distorted analog signal,

the distorted analog signal is a signal that is distorted by an analog element in the DAC and output from the DAC circuit, when a predetermined input digital signal is input to the DAC circuit without passing through the subtraction section.

2. The DAC device of claim 1 , wherein

the analog element in the DAC circuit is at least one selected from the group consisting of a resistance of wiring connecting the DAC circuit to a predetermined power supply, a resistance of wiring connecting the DAC circuit to a GND power supply, a resistance of an internal switch, and an output resistance.

3. The DAC device of claim 1 , wherein

the correction value output section includes:

a memory configured to store a correlation between each of input sections obtained by dividing an entire input section corresponding to an input voltage range of the input digital signal of the DAC device in the distortion correction function, and a correction value based on the distortion correction function that is predetermined for the corresponding one of the input sections; and

a nonlinear correction circuit configured to receive the input digital signal, read a correction value corresponding to the received digital signal from the memory section, and output the correction value to the subtraction section.

4. The DAC device of claim 3 , wherein

the memory stores a plurality of distortion correction functions in accordance with a voltage range of a digital signal to be input.

5. The DAC device of claim 3 , wherein

the memory includes a look-up table that stores a correlation between each of the input sections and a corresponding correction value.

6. The DAC device of claim 3 , wherein

the entire input section of the distortion correction function in the memory is evenly divided into the plurality of input sections.

7. The DAC device of claim 3 , wherein

the entire input section of the distortion correction function in the memory is divided into the plurality of input sections such that a width of the input sections decreases as a degree of change in the distortion correction function increases.

8. The DAC device of claim 6 , wherein

the correction value is determined such that a distortion component included in an analog signal output from the DAC circuit is close to zero at a maximum distortion point and a minimum distortion point of the distortion correction function in the memory.

9. The DAC device of claim 6 , wherein

the correction value is determined such that a distortion component included in the analog signal output from the DAC circuit is close to zero at a maximum distortion point and a minimum distortion point of the distortion correction function in the memory.

10. The DAC device of claim 3 , wherein

the entire input section of the distortion correction function in the memory section is divided into the plurality of input sections such that an amount of change in distortion of the distortion correction function is uniform among the plurality of input.

11. The DAC device of claim 10 , wherein

the correction value is determined such that a distortion component included in the analog signal output from the DAC circuit is close to zero at a maximum distortion point and a minimum distortion point of the distortion correction function in the memory.

12. The DAC device of claim 10 , wherein

the correction value is determined such that a distortion component included in the analog signal output from the DAC circuit is zero at a maximum distortion point and a minimum distortion point of the distortion correction function in the memory.

13. The DAC device of claim 1 , wherein

the correction value output section is a computing section that receives the input digital signal, and based on the received digital signal and the distortion correction function, obtains a correction value to be output to the subtraction section.

14. The DAC device of claim 13 , wherein

the computing section switches the distortion correction function to be used by the computing section, in accordance with a voltage range of a digital signal to be input.

15. An audio system comprising:

the DAC device of claim 1 ;

a loudspeaker; and

a signal processing circuit, wherein

an audio signal converted to an analog signal by the DAC device is output from the loudspeaker through the signal processing circuit.

16. The DAC device of claim 1 , further comprising:

a digital filter configured to multiply a sampling frequency of the input digital signal by n (where n≧2);

a noise shaper configured to receive an output from the digital filter and change frequency characteristics of noise to predetermined characteristics together with word length limitation;

a decoder configured to receive an output from the noise shaper as an input and convert the received output to a 1-bit signal series in accordance with a value of the input;

a 1-bit DAC row configured to convert an output from the decoder to an analog signal; and

an analog adder configured to obtain a sum of outputs from the 1-bit DAC row, wherein

the output from the decoder is determined such that the number of 1-bit signals is cyclic in accordance with a value of the output from the noise shaper.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2014
From: TORII, TOSHIHIRO; HORII, YOSHIHIRO; UCHIDA, MASASHI; NAKATSUKA, JUNJI; SATO, TAKAAKI
To: PANASONIC CORPORATION
Reel/Frame 033043/0728 →