IP Library Granted Patent US 10,916,203
Granted Patent B2
US 10,916,203 · App. 14/209,244 · Granted Feb 9, 2021

Display apparatus

Inventor: Hitoshi Tsuge (Osaka, JP)
Assignee: JOLED INC
G09G3/3291G09G3/3225G09G3/2081G09G2300/0819G09G2300/0852G09G2300/0861G09G2310/0251G09G2310/0262G09G2320/0233G09G2320/0285G09G2320/043G09G2330/021G09G2360/16
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,916,203
App. No.
14/209,244
Granted
Feb 9, 2021
Kind
B2
Abstract

A display apparatus has an image display unit having a plurality of arrayed pixel circuits, and an image signal compensation circuit compensating an image signal and outputs the compensated signal to the image display unit. Each of the pixel circuits has a compensating capacitor which compensates the threshold voltage of the driving transistor. The image signal compensation circuit has a compensation memory storing a compensation data for compensating the current variation of the driving transistors, a first comparison circuit which compares the image signal and first threshold value, and an arithmetic circuit compensating the image signal. When the image signal has a luminance larger than the threshold value, the compensation is performed.

Claims (36)

1. A display apparatus comprising:

an image display unit having a plurality of arrayed pixel circuits; and

an image signal compensation circuit coupled to the image display unit, wherein:

each of the pixel circuits includes:

a current light emitting device;

a driving transistor supplying a current to the current light emitting device; and

a compensating capacitor which is disposed between a gate and a source of the driving transistor, and compensates a threshold voltage of the driving transistor,

the image signal compensation circuit includes:

a compensation memory storing compensation data for compensating mobility dispersion among driving transistors of the plurality of arrayed pixel circuits, the compensation data being for all of the plurality of arrayed pixel, the compensation memory being configured by a frame memory;

a comparison circuit which compares an image signal with a threshold value of luminance; and

an arithmetic circuit which outputs a compensated image signal being compensated by using the compensation data read from the compensation memory,

the comparison circuit outputs an enabling signal to the compensation memory and the arithmetic circuit when the image signal has a luminance larger than the threshold value,

the compensation data is output from the compensation memory to the arithmetic circuit according to the enabling signal, and

the image signal compensation circuit outputs the compensated image signal to the image display unit when the image signal has the luminance larger than the threshold value, and outputs the image signal to the image display unit when the image signal has a luminance smaller than the threshold value.

2. The display apparatus of claim 1 , wherein:

the compensation memory stores compensation data for compensating variation of current in the driving transistors,

the image signal compensation circuit further comprises

a lighting ratio calculation circuit calculating a lighting ratio of the plurality of arrayed pixel circuits for every frame of the image signal,

the comparison circuit comprises:

a first comparison circuit comparing the image signal and a first threshold of luminance; and

a second comparison circuit comparing the lighting ratio calculated by the lighting ratio calculation circuit and a second threshold which is different from the first threshold,

wherein the image signal compensation circuit compensates the image signal when the image signal is larger than the first threshold and the lighting ratio is larger than the second threshold.

3. The display apparatus of claim 1 , wherein:

each of the pixel circuits further comprises:

a first capacitor having a first terminal connected to a gate of the driving transistor;

a second capacitor connected between a second terminal of the first capacitor and a source of the driving transistor;

a first switch applying a reference voltage to a node to which the first and the second capacitors are connected;

a second switch supplying an image signal voltage to the gate of the driving transistor;

a third switch supplying an initialization voltage to drain of the driving transistor; and

a fourth switch supplying current to the drain of the driving transistor for emitting light from the current light emitting device, and

the second capacitor is the compensating capacitor.

4. The display apparatus of claim 1 , wherein the comparison circuit further comprises a logic AND circuit for receiving output signals from the first comparison circuit and the second comparison circuit.

5. The display apparatus of claim 4 , wherein:

the logic AND circuit outputs an enabling signal to the compensation memory and the arithmetic circuit, and

the compensation data is output from the compensation memory to the arithmetic circuit according to the enabling signal.

6. The display apparatus of claim 1 , wherein each of the compensation data for a given driving transistor is calculated from a ratio between a mobility of the given driving transistor and a mobility of a standard driving transistor.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2015
From: PANASONIC CORPORATION
To: JOLED INC
Reel/Frame 035187/0483 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2014
From: TSUGE, HITOSHI
To: PANASONIC CORPORATION
Reel/Frame 033043/0711 →