Low density parity check (LDPC) encoding and decoding for small terminal applications
View Patent ↗Approaches are provided for closing communications channel links (e.g., for small terminal applications in satellite communications systems), at lower effective data rates, in a most power efficient manner, while still meeting regulatory requirements. Such approaches employ modulation and coding schemes that facilitate such lower effective data rates in a most power efficient manner. The new modulation and coding schemes include new low density parity check (LDPC) codes.
1. A method comprising:
encoding, by a processor of a device, a source data sequence of information bits based on a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code, wherein the encoding is performed based on frames of the source data sequence, each frame being of a length of k ldpc information bits (i 0 , i 1 , . . . , i k ldpc −1 ), and the output of the encoding comprises coded LDPC frames each being n ldpc coded bits in length, and
wherein the structured parity check matrix is represented by tabular information of a format wherein each row represents occurrences of one values within a respective column of the parity check matrix, and the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the tabular information, and wherein the tabular information comprises a one of Tables 1a through 1f (below);
TABLE 1a
Address of Parity Bit Accumulators (Rate 1/9, N = 7200)
481 2296 2997 3471 6042 1906 3776 661 6132
1538 4273 361 3175 2055 6040 924 6092 3272
25 1855 3580 4140 3368 37 4336 439 594
4192 1604 3152 2402 1146 2580 3629 5341 3498
1631 1029 3401
4541 4945 5399
2937 5709 2532
6273 5770 1519
TABLE 1b
Address of Parity Bit Accumulators
(Rate 2/9, N = 7200)
4557 3588 3053 538 1502 5541 2801
675 4275 1415 216 10 2497 5112
1615 1453 4656 2570 5189 4299 2737
28 4142 2786 1110 2249 4969 3866
1034 2067 2625 1368 3853 4311 4007
4492 466 275 2104 1145 4227 3937
5302 1029 1243 807 884 4743 3812
294 2895 2004 756 2445 3271 1870
4169 1411 3840
4654 3710 2684
3877 2448 3738
4933 3838 4778
484 2753 4431
3080 1024 2275
427 4202 646
4536 2135 2820
TABLE 1c
Address of Parity Bit Accumulators
(Rate 3/9, N = 7200)
1861 1874 3520 3810 1131 4520
4240 667 4548 4529 1593 3641
4334 2781 3360 2119 738 2254
3911 3674 1190 709 4191 3217
117 1009 1614 4367 3312 4406
2338 1288 2963 688 1468 2621
1374 1448 4186 1017 143 3197
4402 3009 4304 4295 984 4217
4238 3832 549 1644 2749 2678
1598 1520 1839 4743 157 1948
4179 1979 1719 1856 4418 2179
1617 1816 3506 4702 3483 4518
511 3674 2538 30 3511 3462
4602 1140 1658 1375 3286 3875
821 3597 4036 457 438 3454
3988 4006 1914 3859 2300 4164
2213 1347 265
2364 3896 1344
1554 3524 2530
4193 166 2314
491 346 940
4276 2940 4680
1556 2300 168
1124 4555 1916
TABLE 1d
Address of Parity Bit Accumulators
(Rate 4/9, N = 7200)
2008 293 3872 167 1594
3813 1424 609 2395 1506
1743 2092 224 713 2779
2637 1184 2116 2442 2654
3216 2706 834 303 715
3660 402 281 2267 2709
2370 196 2745 1440 1641
205 869 969 1602 2455
500 746 473 2083 401
2363 2407 949 3080 2798
2508 3754 1843 2140 3094
3718 3841 1840 1981 2912
2924 3635 3716 1694 1101
89 3706 3127 355 3277
2340 1983 1277 683 3085
2053 1470 1113 137 2126
112 2781 3480 290 3611
3845 2772 3135 1663 3785
3270 1519 1930 2507 1236
3416 3907 3181 3213 2139
2644 2211 1799 158 591
1137 2645 3858 3884 1113
1975 3732 3417 3942 2570
708 2151 2179 2776 2302
566 3070 2455
3982 191 3388
618 2748 318
3871 1898 456
3688 1818 1665
2785 768 79
2568 3851 2966
3086 1531 3230
TABLE 1e
Address of Parity Bit Accumulators
(Rate 5/9, N = 7200)
22 1372 2500 1497 3032
2824 723 2075 3183 3122
1608 713 1500 653 436
19 409 2086 1634 544
51 2956 270 1918 1201
1067 464 175 753 2110
2978 1416 102 2352 485
1446 1846 1934 939 2781
777 1330 2608 456 766
2861 228 1863 1248 2525
2606 453 2538 2844 1437
1044 1177 1047 98 2259
3128 193 2673 15 311
874 3060 78 2231 1979
21 1699 2487 712 1678
1802 3143 2051 3017 1052
205 3166 787 66 3077
2194 2314 3034 2344 1311
432 1679 1866 359 2476
807 817 534 3090 317
2916 724 2905 1484 2623
2697 373 901 1853 2019
1766 2373 1178 214 3089
1658 2786 1976 896 3199
737 1301 2300
1761 3195 476
1202 441 3081
1991 36 3008
2586 13 1120
1796 1883 2712
570 1407 2743
1630 3000 2811
504 1900 2512
2340 847 1718
2477 1798 1667
2356 1232 1411
971 1600 2271
853 1259 2932
629 140 929
321 1323 2508
TABLE 1f
Address of Parity Bit Accumulators
(Rate 6/9, N = 7200)
1748 1999 1640 1186 2169
1524 1385 355 1206 69
306 221 1341 1192 527
878 609 787 438 1841
359 1676 737 345 624
948 2037 2380 880 2010
1086 36 820 2297 635
496 1704 59 281 2334
1981 323 1318 1731 436
237 2198 418 13 1848
1973 106 142 1864 1155
424 2237 401 1990 2280
254 997 473 1799 102
1122 1894 1095 280 2177
2093 230 1495 1689 307
1872 1053 349 242 619
1965 1636 878 843 2305
1957 1869 2170 1491 1478
675 1521 2047 947 1346
374 405 746 639 2227
804 2296 853 2072 361
372 2259 2306 1867 479
191 558 1609 931 2196
372 1 681 1942 1388
2095 2127 1992
3 461 830
24 1069 1163
1033 822 1634
656 438 1503
721 135 2170
865 1419 1288
964 1453 1297
1536 2086 1100
1778 391 1291
1068 1655 365
410 419 1784
1949 1130 2095
2164 1338 236
1733 82 2038
1895 439 622
599 2338 2171
2047 642 260
868 572 800
1955 224 1329
2372 1818 56
656 594 2271
759 1426 1074
1852 1353 1671.
2. The method of claim 1 , wherein the encoding comprises generating n ldpc −k ldpc parity bits (p 0 , p 1 , . . . , p n ldpc −k ldpc −1 ) for each frame of the source data sequence, wherein the generation of the parity bits comprises:
initializing parity bit accumulators for p 0 , p 1 , . . . , p n ldpc −k ldpc −1 to zero;
accumulating information bit i 0 at parity bit accumulator addresses specified in the first row of the table;
for the next group of M−1 information bits, i y (y=1, 2, . . . , M−1), accumulating each information bit at parity bit accumulator addresses {x+(y mod M)*q} mod (n ldpc −k ldpc ), wherein x denotes an address of a parity bit accumulator corresponding to the information bit i 0 , and wherein q and M are code-dependent constants and k=R*n (where R is the code rate);
accumulating i M at parity bit accumulator addresses specified in the second row of the table, and, in a similar manner as for the group of M−1 information bits (above), accumulating each information bit of the next group of M−1 information bits i z , z=(M+1, M+2, . . . , 2M−1) at parity bit accumulator addresses {x+(z mod M)*q} mod (n ldpc −k ldpc ), wherein x denotes the address of the parity bit accumulator corresponding to the information bit i M (the entries of the second row of the table);
in a similar manner, for each subsequent group of M information bits, accumulating the information bits at parity bit addresses based on a next row of the table; and
after all of the information bits of the frame are accumulated, performing operations according to p i =p i ⊕p i−1 , wherein for i=1, 2, . . . , (n ldpc −k ldpc −1), each p i resulting from the operation for a given i is equal to the parity bit p i .
3. The method of claim 2 , wherein, for a given LDPC code rate, the q and M values are in accordance with the following table:
Rate
M
q
1/9
100
64
2/9
100
56
3/9
100
48
4/9
100
40
5/9
100
32
6/9
100
24.
4. The method of claim 1 , wherein the LDPC code is of a structure that facilitates use of a plurality of parallel engines for decoding the coded signal.
5. The method of claim 1 , further comprising:
modulating the coded LDPC frames according to according to one of the following modulation types: BPSK (Binary Phase Shift Keying), π/2 BPSK, OQPSK (Offset Quadrature Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8-PSK (Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying), 32-APSK, 64-APSK and 256-APSK.
6. The method of claim 1 , wherein the source data sequence is segmented into a series of baseband frames, and the method further comprises:
encoding each baseband frame based on a t-error Bose Chaudhuri Hocquenghem (BCH) code, wherein the BCH encoding comprises an outer coding and the LDPC encoding comprises an inner coding.
7. The method of claim 1 , further comprising:
interleaving each coded LDPC frame using a block interleaver, and the output of the interleaving comprises coded FEC frames.
8. An apparatus comprising:
at least one processor; and
at least one memory including computer program code for one or more programs,
the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following:
encoding a source data sequence of information bits based on a predetermined structured parity check matrix of a Low Density Parity Check (LDPC) code, wherein the encoding is performed based on frames of the source data sequence, each frame being of a length of k ldpc information bits (i 0 , i 1 , . . . , i k ldpc −1 ), and the output of the encoding comprises coded LDPC frames each being n ldpc coded bits in length, and
wherein the structured parity check matrix is represented by tabular information of a format wherein each row represents occurrences of one values within a respective column of the parity check matrix, and the columns of the parity check matrix are derived according to a predetermined operation based on the respective rows of the tabular information, and wherein the tabular information comprises a one of Tables 8a through 8f (below);
TABLE 8a
Address of Parity Bit Accumulators
(Rate 1/9, N = 7200)
481 2296 2997 3471 6042 1906 3776 661 6132
1538 4273 361 3175 2055 6040 924 6092 3272
25 1855 3580 4140 3368 37 4336 439 594
4192 1604 3152 2402 1146 2580 3629 5341 3498
1631 1029 3401
4541 4945 5399
2937 5709 2532
6273 5770 1519
TABLE 8b
Address of Parity Bit Accumulators
(Rate 2/9, N = 7200)
4557 3588 3053 538 1502 5541 2801
675 4275 1415 216 10 2497 5112
1615 1453 4656 2570 5189 4299 2737
28 4142 2786 1110 2249 4969 3866
1034 2067 2625 1368 3853 4311 4007
4492 466 275 2104 1145 4227 3937
5302 1029 1243 807 884 4743 3812
294 2895 2004 756 2445 3271 1870
4169 1411 3840
4654 3710 2684
3877 2448 3738
4933 3838 4778
484 2753 4431
3080 1024 2275
427 4202 646
4536 2135 2820
TABLE 8c
Address of Parity Bit Accumulators
(Rate 3/9, N = 7200)
1861 1874 3520 3810 1131 4520
4240 667 4548 4529 1593 3641
4334 2781 3360 2119 738 2254
3911 3674 1190 709 4191 3217
117 1009 1614 4367 3312 4406
2338 1288 2963 688 1468 2621
1374 1448 4186 1017 143 3197
4402 3009 4304 4295 984 4217
4238 3832 549 1644 2749 2678
1598 1520 1839 4743 157 1948
4179 1979 1719 1856 4418 2179
1617 1816 3506 4702 3483 4518
511 3674 2538 30 3511 3462
4602 1140 1658 1375 3286 3875
821 3597 4036 457 438 3454
3988 4006 1914 3859 2300 4164
2213 1347 265
2364 3896 1344
1554 3524 2530
4193 166 2314
491 346 940
4276 2940 4680
1556 2300 168
1124 4555 1916
TABLE 8d
Address of Parity Bit Accumulators
(Rate 4/9, N = 7200)
2008 293 3872 167 1594
3813 1424 609 2395 1506
1743 2092 224 713 2779
2637 1184 2116 2442 2654
3216 2706 834 303 715
3660 402 281 2267 2709
2370 196 2745 1440 1641
205 869 969 1602 2455
500 746 473 2083 401
2363 2407 949 3080 2798
2508 3754 1843 2140 3094
3718 3841 1840 1981 2912
2924 3635 3716 1694 1101
89 3706 3127 355 3277
2340 1983 1277 683 3085
2053 1470 1113 137 2126
112 2781 3480 290 3611
3845 2772 3135 1663 3785
3270 1519 1930 2507 1236
3416 3907 3181 3213 2139
2644 2211 1799 158 591
1137 2645 3858 3884 1113
1975 3732 3417 3942 2570
708 2151 2179 2776 2302
566 3070 2455
3982 191 3388
618 2748 318
3871 1898 456
3688 1818 1665
2785 768 79
2568 3851 2966
3086 1531 3230
TABLE 8e
Address of Parity Bit Accumulators
(Rate 5/9, N = 7200)
22 1372 2500 1497 3032
2824 723 2075 3183 3122
1608 713 1500 653 436
19 409 2086 1634 544
51 2956 270 1918 1201
1067 464 175 753 2110
2978 1416 102 2352 485
1446 1846 1934 939 2781
777 1330 2608 456 766
2861 228 1863 1248 2525
2606 453 2538 2844 1437
1044 1177 1047 98 2259
3128 193 2673 15 311
874 3060 78 2231 1979
21 1699 2487 712 1678
1802 3143 2051 3017 1052
205 3166 787 66 3077
2194 2314 3034 2344 1311
432 1679 1866 359 2476
807 817 534 3090 317
2916 724 2905 1484 2623
2697 373 901 1853 2019
1766 2373 1178 214 3089
1658 2786 1976 896 3199
737 1301 2300
1761 3195 476
1202 441 3081
1991 36 3008
2586 13 1120
1796 1883 2712
570 1407 2743
1630 3000 2811
504 1900 2512
2340 847 1718
2477 1798 1667
2356 1232 1411
971 1600 2271
853 1259 2932
629 140 929
321 1323 2508
TABLE 8f
Address of Parity Bit Accumulators
(Rate 6/9, N = 7200)
1748 1999 1640 1186 2169
1524 1385 355 1206 69
306 221 1341 1192 527
878 609 787 438 1841
359 1676 737 345 624
948 2037 2380 880 2010
1086 36 820 2297 635
496 1704 59 281 2334
1981 323 1318 1731 436
237 2198 418 13 1848
1973 106 142 1864 1155
424 2237 401 1990 2280
254 997 473 1799 102
1122 1894 1095 280 2177
2093 230 1495 1689 307
1872 1053 349 242 619
1965 1636 878 843 2305
1957 1869 2170 1491 1478
675 1521 2047 947 1346
374 405 746 639 2227
804 2296 853 2072 361
372 2259 2306 1867 479
191 558 1609 931 2196
372 1 681 1942 1388
2095 2127 1992
3 461 830
24 1069 1163
1033 822 1634
656 438 1503
721 135 2170
865 1419 1288
964 1453 1297
1536 2086 1100
1778 391 1291
1068 1655 365
410 419 1784
1949 1130 2095
2164 1338 236
1733 82 2038
1895 439 622
599 2338 2171
2047 642 260
868 572 800
1955 224 1329
2372 1818 56
656 594 2271
759 1426 1074
1852 1353 1671.
9. The apparatus of claim 8 , wherein the encoding comprises generating n ldpc −k ldpc parity bits (p 0 , p 1 , . . . , p n ldpc −k ldpc −1 ) for each frame of the source data sequence, wherein the generation of the parity bits comprises:
initializing parity bit accumulators for p 0 , p 1 , . . . , p n ldpc −k ldpc −1 to zero;
accumulating information bit i 0 at parity bit accumulator addresses specified in the first row of the table;
for the next group of M−1 information bits, i y (y=1, 2, . . . , M−1), accumulating each information bit at parity bit accumulator addresses {x+(y mod M)*q} mod (n ldpc −k ldpc ), wherein x denotes an address of a parity bit accumulator corresponding to the information bit i 0 , and wherein q and M are code-dependent constants and k=R*n (where R is the code rate);
accumulating i M at parity bit accumulator addresses specified in the second row of the table, and, in a similar manner as for the group of M−1 information bits (above), accumulating each information bit of the next group of M−1 information bits i z , z=(M+1, M+2, . . . , 2M−1) at parity bit accumulator addresses {x+(z mod M)*q} mod (n ldpc −k ldpc ), wherein x denotes the address of the parity bit accumulator corresponding to the information bit i M (the entries of the second row of the table);
in a similar manner, for each subsequent group of M information bits, accumulating the information bits at parity bit addresses based on a next row of the table; and
after all of the information bits of the frame are accumulated, performing operations according to p i =p i ⊕p i−1 , wherein for i=1, 2, . . . , (n ldpc −k ldpc −1), each p i resulting from the operation for a given i is equal to the parity bit p i .
10. The apparatus of claim 9 , wherein, for a given LDPC code rate, the q and M values are in accordance with the following table:
Rate
M
q
1/9
100
64
2/9
100
56
3/9
100
48
4/9
100
40
5/9
100
32
6/9
100
24.
11. The apparatus of claim 8 , wherein the LDPC code is of a structure that facilitates use of a plurality of parallel engines for decoding the coded signal.
12. The apparatus of claim 8 , wherein the apparatus is further caused to perform:
modulating the coded LDPC frames according to according to one of the following modulation types: BPSK (Binary Phase Shift Keying), π/2 BPSK, OQPSK (Offset Quadrature Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8-PSK (Phase Shift Keying), 16-APSK (Amplitude Phase Shift Keying), 32-APSK, 64-APSK and 256-APSK.
13. The apparatus of claim 8 , wherein the source data sequence is segmented into a series of baseband frames, and the apparatus is further caused to perform:
encoding each baseband frame based on a t-error Bose Chaudhuri Hocquenghem (BCH) code, wherein the BCH encoding comprises an outer coding and the LDPC encoding comprises an inner coding.
14. The apparatus of claim 8 , wherein the apparatus is further caused to perform:
interleaving each coded LDPC frame using a block interleaver, and the output of the interleaving comprises coded FEC frames.