Data transformations to improve ROM yield and programming time
View Patent ↗Methods and systems for generating data transformations to improve ROM yield and programming time. A bit flip register can be configured in association with the ROM and a binary string can be read into the bit flip register on reset. Subsequently, data output from the ROM can be selectively complemented utilizing a content of the bit flip register and the content of the bit flip register can be programmed into the ROM in order to reduce programming time for each ROM. A defective cell can be tolerated by selectively flipping a column with respect to the defective cell to improve yield. A built-in self-test (BIST) engine that generates addresses up to and including content of an address limiting register can be employed to limit the ROM access to a programmed part during testing in order to tolerate defects in any unused location.
1. A method of generating data transformations to improve ROM yield and programming time, said method comprising:
configuring a bit flip register in association with a ROM and thereafter reading a binary string into said it flip register upon reset;
selectively complementing data output from said ROM utilizing a content of said bit flip register and programming said content of said bit flip register into said ROM in order to reduce a programming time with respect to each ROM;
tolerating a defective cell by selectively flipping a column with respect to a defective cell to improve a yield with respect to said ROM; and
limiting said ROM access to a programmed part during a test run in order to tolerate a defect in an unused location utilizing a ROM built-in self test engine that generates addresses up to and including a content of an address limiting register.
2. The method of claim 1 further comprising modifying an image header by adding a base address field that includes a start address of a remaining portion of a header and a read-only memory (ROM) image to simultaneously reduce said ROM programming time and increase said ROM yield.
3. The method of claim 1 further comprising flipping said bits to cover said defect and thereafter flip a remaining selective bit to reduce said ROM programming time.
4. The method of claim 1 further comprising accessing a programmed part of said ROM in a functional mode and limiting said ROM access to said programmed part during said test run.
5. The method of claim 1 further comprising:
generating an address up to and including said content of said address limiting register utilizing an address generator with respect to said ROM built-in self test engine; and
compressing an output of said ROM into a multiple-input signature register.
6. The method of claim 5 further comprising:
comparing a signature stored in said multiple-input signature register with a gold signature which is stored in a last utilized location of said ROM at an end of said test run; and
limiting access of said ROM only within a region where said ROM is programmed so that said ROM built-in self test engine never accesses said defective cell.
7. The method of claim 1 further comprising:
clearing an REL address register and loading a base address bit and a bit flip register bit, respectively, into said base address register and said bit flip register; and
summing said REL address register and said base address register to obtain subsequent addresses generated for said ROM access.
8. A system of generating data transformations to improve ROM yield and programming time, said system comprising:
a processor; and
a computer-usable medium embodying computer program code, said computer-usable medium capable of communicating with the processor, said computer program code comprising instructions executable by said processor and configured for:
configuring a bit flip register in association with a ROM and thereafter reading a binary string into said bit flip register upon reset;
selectively complementing data output from said ROM utilizing a content of said bit flip register and programming said content of said bit flip register into said ROM in order to reduce a programming time with respect to each ROM;
tolerating a defective cell by selectively flipping a column with respect to a defective cell to improve a yield with respect to said ROM; and
limiting said ROM access to a programmed part during a test run in order to tolerate a defect in an unused location utilizing a ROM built-in self test engine that generates addresses up to and including a content of an address limiting register.
9. The system of claim 8 wherein said instructions are further configured for modifying an image header by adding a base address field that includes a start address of a remaining portion of a header and a ROM image to simultaneously reduce said ROM programming time and increase said ROM yield.
10. The system of claim 8 wherein said instructions are further configured for flipping said bits to cover said defect and thereafter flip a remaining selective bit to reduce said ROM programming time.
11. The system of claim 8 wherein said instructions are further configured for:
accessing a programmed portion of said ROM in a functional mode; and
limiting said ROM access to said programmed portion during said test run.
12. The system of claim 8 wherein said instructions are further configured for:
generating an address up to and including said content of said address limiting register utilizing an address generator with respect to said ROM built-in self test engine; and
compressing an output of said ROM into a multiple-input signature register.
13. The system of claim 12 wherein said instructions are further configured for:
comparing signature stored in said multiple-input signature register with a gold signature which is stored in a last utilized location of said ROM at an end of said test run; and
limiting access of said ROM only within a region where said ROM is programmed so that said ROM built-in self test engine never accesses said defective cell.
14. The system of claim 8 wherein said instructions are further configured for:
clearing a REL address register and loading a base address bit and a bit flip register bit, respectively, into said base address register and said bit flip register; and
summing REL address register and said base address register to obtain subsequent addresses generated for said ROM access.
15. A processor-readable medium storing code representing instructions to cause a process for generating data transformations to improve ROM yield and programming time, said code comprising code to:
configure a bit flip register in association with a ROM and thereafter reading a binary string into said Pit flip register upon reset;
selectively complement data output from said ROM utilizing a content of said bit flip register and program said content of said bit flip register into said ROM in order to reduce a programming time with respect to each ROM;
tolerate a defective cell by selectively flipping a column with respect to a defective cell to improve a yield with respect to said ROM; and
limit said ROM access to a programmed part during a test run in order to tolerate a defect in an unused location utilizing a ROM built-in self test engine that generates addresses up to and including a content of an address limiting register.
16. The processor-readable medium of claim 15 wherein said code further includes code to modify an image header by adding a base address field that includes a start address of a remaining portion of a header and a ROM image to simultaneously reduce said ROM programming time and increase said ROM yield.
17. The processor-readable medium of claim 15 wherein said code further includes code to flip said bits to cover said defect and thereafter flip a remaining selective bit to reduce said ROM programming time.
18. The processor-readable medium of claim 15 wherein said code further includes code to:
access a programmed portion of said ROM in a functional mode; and
limit said ROM access to said programmed portion during said test run.
19. The processor-readable medium of claim 15 wherein said code further includes code to:
generate an address up to and including said content of said address limiting register utilizing an address generator with respect to said ROM built-in self test engine; and
compress an output of said ROM into a multiple-input signature register.
20. The processor-readable medium of claim 19 wherein said code further includes code to:
compare signature stored in said multiple-input signature register with a gold signature which is stored in a last utilized location of said ROM at end of said test run; and
limit access of said ROM only within a region where said ROM is programmed so that said ROM built-in self test engine never accesses said defective cell.