Striping cache blocks with logical block address scrambling
View Patent ↗A method for information handling systems includes receiving a storage operation to be applied to a cache block in a location in a distributed storage system. The location is defined by a logical block address (LBA). The method further includes swapping a first portion of the LBA with a second portion of the LBA, resulting in a modified LBA, and performing the storage operation with the modified LBA. The first portion and the second portion are both x bits wide.
1. A method for information handling systems, comprising:
receiving a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
swapping a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA; and
performing the storage operation with the modified LBA.
2. The method of claim 1 , wherein the second portion of the LBA is from a cache block identifier in the LBA.
3. The method of claim 2 , wherein the second portion includes the lowest x bits of the cache block identifier in the LBA.
4. The method of claim 1 , wherein swapping the first portion of the second portion causes the modified LBA to indicate a different offset and a different cache block identifier than the LBA.
5. The method of claim 1 , wherein memories used to implement the distributed storage system include flash devices of different sizes.
6. The method of claim 1 :
wherein upon a failure of a node within the distributed storage system, the results of the storage operation are persistently stored in one or more attached memory devices and are available for client access; and
further comprising, after the failure of the node within the distributed storage system:
providing read and write access for clients to the results of the storage operation; and
replicating the results of the storage operation to another location within the distributed storage system.
7. The method of claim 1 , further comprising concurrently allowing a first access and a second access to a logical unit including the results of the storage operation, the first access and the second access each including a read or write operation.
8. The method of claim 1 , wherein:
the cache block is included in a plurality of cache blocks of a logical unit; and
the method further comprises provisioning the logical unit without use of auxiliary storage for flushing.
9. The method of claim 1 , wherein:
the cache block is implemented in a first attached memory;
the distributed storage system comprises a second cache block implemented in a second cache memory; and
the method further comprises adding or removing the second cache memory while the storage operation is received and performed.
10. An article of manufacture, comprising:
a non-transitory machine-readable medium; and
instructions on the computer-readable medium, when read by a processor, are configured to cause the processor to:
receive a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
swap a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA; and
perform the storage operation with the modified LBA.
11. The article of claim 10 , wherein the second portion of the LBA is from a cache block identifier in the LBA.
12. The article of claim 11 , wherein the second portion includes the lowest x bits of the cache block identifier in the LBA.
13. The article of claim 10 , wherein swapping the first portion of the second portion causes the modified LBA to indicate a different offset and a different cache block identifier than the LBA.
14. The article of claim 10 , wherein memories used to implement the distributed storage system include flash devices of different sizes.
15. The article of claim 10 :
wherein upon a failure of a node within the distributed storage system, the results of the storage operation are persistently stored in one or more attached memory devices and are available for client access; and
the processor is further configured to, after the failure of the node within the distributed storage system:
provide read and write access for clients to the results of the storage operation; and
replicate the results of the storage operation to another location within the distributed storage system.
16. The article of claim 10 , wherein the processor is further configured to concurrently allow a first access and a second access to a logical unit including the results of the storage operation, the first access and the second access each including a read or write operation.
17. The article of claim 10 , wherein:
the cache block is included in a plurality of cache blocks of a logical unit; and
the processor is further configured to provision the logical unit without use of auxiliary storage for flushing.
18. The article of claim 10 , wherein:
the cache block is implemented in a first attached memory;
the distributed storage system comprises a second cache block implemented in a second cache memory; and
the processor is further configured to add or remove the second cache memory while the storage operation is received and performed.
19. An information handling system, comprising:
a processor;
a machine-readable medium comprising instructions, when read and executed by the processor, are configured to cause the processor to:
receive a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
swap a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA; and
perform the storage operation with the modified LBA.
20. The information handling system of claim 19 , wherein the second portion of the LBA is from a cache block identifier in the LBA.
21. The information handling system of claim 20 , wherein the second portion includes the lowest x bits of the cache block identifier in the LBA.
22. The information handling system of claim 19 , wherein swapping the first portion of the second portion causes the modified LBA to indicate a different offset and a different cache block identifier than the LBA.
23. The information handling system of claim 19 :
wherein upon a failure of a node within the distributed storage system, the results of the storage operation are persistently stored in one or more attached memory devices and are available for client access; and
the processor is further configured to, after the failure of the node within the distributed storage system:
provide read and write access for clients to the results of the storage operation; and
replicate the results of the storage operation to another location within the distributed storage system.
24. The information handling system of claim 19 , wherein the processor is further configured to concurrently allow a first access and a second access to a logical unit including the results of the storage operation, the first access and the second access each including a read or write operation.
25. The information handling system of claim 19 , wherein:
the cache block is included in a plurality of cache blocks of a logical unit; and
the processor is further configured to provision the logical unit without use of auxiliary storage for flushing.
26. The information handling system of claim 19 , wherein:
the cache block is implemented in a first attached memory;
the distributed storage system comprises a second cache block implemented in a second cache memory; and
the processor is further configured to add or remove the second cache memory while the storage operation is received and performed.